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--- projects:cordic_algorithm [2013/12/19 21:59]
cbarnes
+++ projects:cordic_algorithm [2013/12/19 23:19] (current)
cbarnes
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 Made by: Claire Barnes
 ====  What did you do?  ====
-For my final project, I decided to implement the CORDIC algorithm in Verilog. The CORDIC algorithm implements trigonometric, hyperbolic, and logarithmic functions in digital logic using only bit-shifts, additions (and subtractions), and one look up table. I was only able to implement the sine and cosine functions. My reach goal was to implement log in any base, but I did not have time. So I focused on sine and cosine and creating a program that could input a given angle and output the sine and cosine of that angle.
+For my final project, I decided to implement the CORDIC algorithm in Verilog. The CORDIC algorithm implements trigonometric, hyperbolic, and logarithmic functions in digital logic using only bit-shifts, additions (and subtractions), and one look up table. I was only able to implement the sine and cosine functions. My reach goal was to implement log in any base, but I did not have time. So I focused on sine and cosine and creating a program that could input a given angle and output the sine and cosine of that angle. Currently, it only works on angles between 0 and 90 degrees.
 ====  Why did you do it?  ====
 When I first heard about the CORDIC algorithm, I thought it was too good to be true. A way to calculate all these crazy functions without doing a single multiply? How could that be? So I was intrigued and I decided to do my project on that.
@@ Line 15: / Line 16: @@
 === Verilog ===
-Finally, I was ready (or at least, as ready as I ever would be) to make CORDIC in verilog. Fortunately, people had done similar things and shared their work on the internet, so even though I am on a team by myself, I certainly didn't have no help. I started by making the simple module, defining x, y, and angle inputs and sine/cosine outputs. Then I had to produce a 31-entry long table of atan values to be my look-up-table. Each value in the table is equivalent to atan(2<sup>-i</sup>) where i starts at 0 and ends at 30.
+Finally, I was ready (or at least, as ready as I ever would be) to make CORDIC in verilog. Fortunately, people had done similar things and shared their work on the internet, so even though I am on a team by myself, I certainly didn't have no help. I started by making the simple module, defining x, y, and angle inputs and sine/cosine outputs.
-=== Music with a LUT ===
+Then I had to produce a 31-entry long table of atan values to be my look-up-table. Each value in the table is equivalent to atan(2<sup>-i</sup>) where i starts at 0 and ends at 30. But, to create a 32-bit scaled value so that all the unsigned, fixed-point arithmetic would work out, every value was multiplied by 2<sup>32</sup> and divided by 360. Thus the atan table was created. {{ :projects:atan_table2.png?700 |}}
-The other mode in which want our FPGA to operate is to play a predetermined song. We wrote verilog code to do this, and while this code synthesizes correctly, we are unable to make it work on the FPGA for presently unknown reasons. The code that does this is in LUT\_song.v, which uses a look up table to read from a mem file that contains instructions for individual notes in the form of seven bit binary strings to denote the seven notes that are mapped to our GPIO pins on the FPGA. Currently, the look up table reads from the master.mem file in the appendix, and uses a frequency divider to play each note of We Wish You a Merry Christmas for about a second long.
+The CORDIC algorithm only works for values between -90 and 90 degrees. This is why my next step was to check if these conditions were true, and make the necessary changes if not. Because of the way I scaled the angles, I could simply check the leading 2 bits to see what quadrant the angle was in. {{ :projects:quadrant.png?700 |}}
-=== Analog Circuit ===
+The last part was to finally implement the meat of the CORDIC algorithm where all the iterations take place that produce cosine and sine values. The number of iterations that need to be implemented depends on how many bits wide the input is. Since my inputs were 16-bits wide, I only needed 16 iterations before I wouldn't be getting any more precision. So the entire algorithm is contained in a for loop that goes though, assigns the bit-shifted X and Y variables of the current iteration, finds the sign of the current Z angle, then calculates the next values of X, Y, and Z. {{ :projects:cordic.png?700 |}}
-In order to have all of our GPIO pins play their notes through the same speaker, we needed to construct a circuit that added the signals together. To accomplish this, we created a simple analog signal-adding circuit. This circuit uses an inverting amplifier to amplify the summed signal.
-The seven GPIO pins which generate the notes' frequencies are each attached to a 1kΩ resistor. These seven resistors are all attached to the noninverting input of the op amp. Note that the op amp pictured is not the one which we opted to use; while we used a TL081, it is fine to use most any op amp. The inverting amplifier has a resistor, Rf, which determines the gain.
-We also connect each GPIO pin to an LED, such that the LED's light up according to the note that we are playing. The notes we are playing are at a frequency high enough that the LED blinks too quickly to be visible to the human eye. As a result, it appears that the LED is always on for any note that is being played.
-====  How can someone else build on it?  ====
-=== Build Instructions: Quickstart ===
-. Download Xilinx ISE design tools at http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html.
-. Clone github repo: https://github.com/mdelrosa/cafinalproject
-. Create a new project in Xilinx (follow instructions from http://tinyurl.com/ca-fpga-13; these next steps outline the process described in the tutorial)
-. Add piano.v as a source
-. Right click on piano.v, click on add source, and add piano.ucf
-. Click on the Green arrow that says "Implement Top Module"; this should synthesize your top level module and implement the design constraints set by the ucf file
-. Double click on "Configure Target Device"
-. Make sure your FPGA is attached to your computer and click on the Boundary Scan button
-. Click on initialize chain; select the .bit file that was generated during synthesis on the first menu that pops up, then click bypass on the second menu
-. Program the chip on the left by right clicking on it and hitting program.
-. If you have not already, build the circuit found in the Analog Circuit subsection. Ensure that the appropriate GPIO pins are attached since the UCF file denotes these specific pins from the FPGA.
-. Use the switches to play different notes/combinations of notes.
 === Difficulties ===
-Our main difficulty was in implementing the music code (i.e., the module that played a simple song).  We managed to synthesize the master.v module and its dependent modules in the Xilinx ISE, but whenever we attempted to configure the target device, we got an un-logged error which prevented us from compiling the code onto the FPGA.
+My main difficulty was understanding and implementing fixed-point, signed arithmetic. Many of the methods I implemented, I learned from other people's work on the internet who had done similar things. So I don't fully understand what those things accomplished or if there was a better way to do it.
 === Future Work ===
-While we did make a piano for our project, we belive that the future of our project would be to make the piano play songs on its own. We had coded a verilog script that used a look up table to instruct which note to play and LEDs to light. The XILINX was able to synthesis the code, but fails when trying to use the target device. This project could be improved by having the piano be able to play some predetermined songs.
+Since the quadrant-checking step seems to not be working, that would be the next step so that sine and cosine work for any input angle. The next logical step would be to implement more trigonometric, logarithmic, and hyperbolic functions.
 === Workplan Reflection ===
-In our workplan, we set a goal to create an audio/visual synthesizer using an FPGA, which we completed by setting up our FPGA that can play notes and light up LED's depending on  In terms of meeting our goals for the demo, we were able to both play music and light up corresponding LED's.
+In my workplan, my goal was to create Verilog code that would implement the CORDIC algorithm and produce sine and cosine values with the reach goal of doing logarithm as well. I almost met my minimum deliverable, but my code does not perfectly do what I had planned it to do. I think I underestimated how difficult it would be to implement signed, fixed-point math.
-With regard to our workplan, we were able to set out to do everything we wanted to do, partly due to the fact that we were relatively vague in what we actually wanted to do with regard to music. The only step that really took significantly longer than we expected to was synthesizing our verilog code on our FPGA. A large reason for this was that it took us almost a week from when we started to even get all the correct Xilinx packages downloaded and properly installed. Other than that, our timing was about what we expected. Our final step was a rather arbitrary "making our music and lights cooler", which we have been iteratively doing over the course of the last week, and we now have a final product that we are more than satisfied with.
-=== Circuit Diagram ===
-{{ :projects:signaladder.png?400 |}}
+I didn't follow my workplan very well. I think there were a lot of contributing factors as to why, namely that it took me longer than expected to understand the CORDIC algorithm. Most notably though, I realize now that verilog is still a language I am very uncomfortable with and this was what made it take so long implement CORDIC in verilog, although I think my understanding of verilog is significantly higher now.
 === Code Appendix ===
-All of our code is in our github repository: https://github.com/mdelrosa/cafinalproject. The ucf files are all responsible for mapping between the FPGA and our verilog code. The relevant code with regard to the user input piano is in piano.ucf, and piano.v, and the code with regard to playing music with a look up table is in music_code.ucf, LUT_song.v, and memory.mem. The code responsible for switching between the modes is in master.ucf and master.v.
+"https://github.com/bunyipc/cordic"

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