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--- projects:cordic_algorithm [2013/12/19 22:49]
cbarnes
+++ projects:cordic_algorithm [2013/12/19 23:19] (current)
cbarnes
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 === Workplan Reflection ===
-In our workplan, we set a goal to create an audio/visual synthesizer using an FPGA, which we completed by setting up our FPGA that can play notes and light up LED's depending on  In terms of meeting our goals for the demo, we were able to both play music and light up corresponding LED's.
+In my workplan, my goal was to create Verilog code that would implement the CORDIC algorithm and produce sine and cosine values with the reach goal of doing logarithm as well. I almost met my minimum deliverable, but my code does not perfectly do what I had planned it to do. I think I underestimated how difficult it would be to implement signed, fixed-point math.
-With regard to our workplan, we were able to set out to do everything we wanted to do, partly due to the fact that we were relatively vague in what we actually wanted to do with regard to music. The only step that really took significantly longer than we expected to was synthesizing our verilog code on our FPGA. A large reason for this was that it took us almost a week from when we started to even get all the correct Xilinx packages downloaded and properly installed. Other than that, our timing was about what we expected. Our final step was a rather arbitrary "making our music and lights cooler", which we have been iteratively doing over the course of the last week, and we now have a final product that we are more than satisfied with.
+I didn't follow my workplan very well. I think there were a lot of contributing factors as to why, namely that it took me longer than expected to understand the CORDIC algorithm. Most notably though, I realize now that verilog is still a language I am very uncomfortable with and this was what made it take so long implement CORDIC in verilog, although I think my understanding of verilog is significantly higher now.
-=== Circuit Diagram ===
-{{ :projects:signaladder.png?400 |}}
 === Code Appendix ===
-All of our code is in our github repository: https://github.com/mdelrosa/cafinalproject. The ucf files are all responsible for mapping between the FPGA and our verilog code. The relevant code with regard to the user input piano is in piano.ucf, and piano.v, and the code with regard to playing music with a look up table is in music_code.ucf, LUT_song.v, and memory.mem. The code responsible for switching between the modes is in master.ucf and master.v.
+"https://github.com/bunyipc/cordic"

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