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--- projects:fpga_note_generator [2013/12/22 23:20]
criley1
+++ projects:fpga_note_generator [2013/12/30 18:27] (current)
criley1
@@ Line 1: / Line 1: @@
+======FPGA Note Generator======
+by Caitlin Riley
 =====What I Did=====
@@ Line 90: / Line 93: @@
 </file>
-The phase accumulator and sine LUT were included in one module generated by the Xilinx CORE generator. I choose to the output of the sine LUT to be 8-bits because I initially planned on using an 8-bit DAC IC. This was called and then the output to the DAC was assigned using a ternary operator that only supplied an output sine wave if a switch was set high, as shown below.
+The phase accumulator and sine LUT were included in one module generated by the Xilinx CORE generator. I chose to have the phase increment value be 26 bits so that the DDS had a frequency resolution of .745. I chose the output of the sine LUT to be 8-bits because I initially planned on using an 8-bit DAC IC. The DDS module was called and then the output to the DAC was assigned using a ternary operator that only supplied an output sine wave if a switch was set high, as shown below.
 <file verilog>
@@ Line 135: / Line 138: @@
 =====Files=====
-{{projects:note_generator_demo_video.zip}}: Video demonstrating the FPGA outputting an A minor scale.
+{{projects:note_generator_demo_video.zip}}: Video demonstrating the FPGA outputting an A natural minor scale.
 {{projects:notegeneratorproject.zip}}: Contains all of the project files.

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