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projects:fpga_note_generator [2013/12/30 18:21] criley1 |
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- | The phase accumulator and sine LUT were included in one module generated by the Xilinx CORE generator. I choose to the output of the sine LUT to be 8-bits because I initially planned on using an 8-bit DAC IC. This was called and then the output to the DAC was assigned using a ternary operator that only supplied an output sine wave if a switch was set high, as shown below. | + | The phase accumulator and sine LUT were included in one module generated by the Xilinx CORE generator. I chose to have the phase increment value be 26 bits so that the DDS had a frequency resolution of .745. I chose the output of the sine LUT to be 8-bits because I initially planned on using an 8-bit DAC IC. The DDS module was called and then the output to the DAC was assigned using a ternary operator that only supplied an output sine wave if a switch was set high, as shown below. |
<file verilog> | <file verilog> |