projects:optimization_of_a_pipelined_cpu
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projects:optimization_of_a_pipelined_cpu [2013/12/20 00:12] bren525 |
projects:optimization_of_a_pipelined_cpu [2013/12/20 00:23] (current) jhanford [Optimizing a Pipelined CPU] |
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| **Brendan Caporaletti, Chelsea Bailey, Jeffrey Hanford** | **Brendan Caporaletti, Chelsea Bailey, Jeffrey Hanford** | ||
| + | Code: [[https://www.dropbox.com/s/2ulskrgce5xltpq/CPU_ResourceFiles.zip]] | ||
| ===== The Vision ===== | ===== The Vision ===== | ||
| Line 102: | Line 103: | ||
| E = C | E = C | ||
| - | {{:projects:pipelinedcpu_v4.0.png?900|}} | + | {{:projects:pipelinedcpu_v4final.png?900|}} |
| - | ===== Timing Analysis ===== | + | |
| - | ==== Version 1 (Original)==== | + | |
| - | Version 1 corresponds to the pipelined CPU we use for our base. It is the CPU we tested by synthesizing using XILINX. The data from that report is as follows: | ||
| - | |||
| - | ^ Phase ^ Clockspeed (ns) ^ | ||
| - | | IF |27.364| | ||
| - | | ID |21.51| | ||
| - | | EX |22.587| | ||
| - | | MEM |27.779| | ||
| - | | WB |<20| | ||
| - | |||
| - | **Throughput:** | ||
| - | ==== Version 2 (MIPS Compliant)==== | ||
| - | ==== Version 3 (Jump Forward)==== | ||
| - | ==== Version 4 (Dynamic Branching)==== | ||
| ===== Reflection ===== | ===== Reflection ===== | ||
projects/optimization_of_a_pipelined_cpu.1387516379.txt.gz · Last modified: 2013/12/20 00:12 by bren525
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