runSynth Project Status
Project File: NoteGeneratorCopy.xise Parser Errors: No Errors
Module Name: runSynth Implementation State: Programming File Generated
Target Device: xc3s1000-5ft256
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
2 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 66 15,360 1%  
Number of 4 input LUTs 183 15,360 1%  
Number of occupied Slices 118 7,680 1%  
    Number of Slices containing only related logic 118 118 100%  
    Number of Slices containing unrelated logic 0 118 0%  
Total Number of 4 input LUTs 226 15,360 1%  
    Number used as logic 183      
    Number used as a route-thru 43      
Number of bonded IOBs 9 173 5%  
Number of RAMB16s 5 24 20%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 3.04      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Dec 16 09:45:32 201402 Warnings (0 new)4 Infos (2 new)
Translation ReportCurrentTue Dec 16 09:53:26 2014000
Map ReportCurrentTue Dec 16 09:53:33 2014003 Infos (3 new)
Place and Route ReportCurrentTue Dec 16 09:53:44 2014000
Power Report     
Post-PAR Static Timing ReportCurrentTue Dec 16 09:53:48 2014005 Infos (0 new)
Bitgen ReportCurrentTue Dec 16 09:54:01 2014001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentTue Dec 16 09:54:01 2014
WebTalk Log FileCurrentTue Dec 16 09:54:06 2014

Date Generated: 12/17/2014 - 16:15:22