Project Statistics |
PROPEXT_xilxSynthMaxFanout_virtex2=100000 |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/SineSynth |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2013-12-15T23:29:22 |
PROP_intWbtProjectID=E5120F5DF98A43D6BAF31F998A21BD90 |
PROP_intWbtProjectIteration=20 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_selectedSimRootSourceNode_behav=work.SineSynth |
PROP_xilxBitgStart_IntDone=true |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3 |
PROP_DevDevice=xc3s1000 |
PROP_DevFamilyPMName=spartan3 |
PROP_DevPackage=ft256 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-5 |
PROP_PreferredLanguage=Verilog |
FILE_NGC=1 |
FILE_UCF=1 |
FILE_VERILOG=2 |