SineSynth Project Status (12/19/2013 - 23:43:38)
Project File: NoteGenerator.xise Parser Errors: No Errors
Module Name: SineSynth Implementation State: Programming File Generated
Target Device: xc3s1000-5ft256
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
31 Warnings (31 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 37 15,360 1%  
Number of 4 input LUTs 37 15,360 1%  
Number of occupied Slices 29 7,680 1%  
    Number of Slices containing only related logic 29 29 100%  
    Number of Slices containing unrelated logic 0 29 0%  
Total Number of 4 input LUTs 52 15,360 1%  
    Number used as logic 37      
    Number used as a route-thru 15      
Number of bonded IOBs 17 173 9%  
Number of RAMB16s 1 24 4%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 2.05      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun Dec 22 23:07:02 2013031 Warnings (31 new)1 Info (1 new)
Translation ReportCurrentSun Dec 22 23:07:27 2013000
Map ReportCurrentSun Dec 22 23:07:53 2013003 Infos (3 new)
Place and Route ReportCurrentSun Dec 22 23:08:23 2013000
Power Report     
Post-PAR Static Timing ReportCurrentSun Dec 22 23:08:35 2013005 Infos (5 new)
Bitgen ReportCurrentSun Dec 22 23:08:58 2013001 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentSun Dec 22 23:09:01 2013
WebTalk Log FileCurrentSun Dec 22 23:09:12 2013

Date Generated: 12/22/2013 - 23:10:33