Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s1000
Project ID (random number) dc251a9d6a3445e0a9ba5dd29347b227.E5120F5DF98A43D6BAF31F998A21BD90.20 Target Package: ft256
Registration ID 210834542_0_0_730 Target Speed: -5
Date Generated 2013-12-22T23:09:01 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-2620M CPU @ 2.70GHz CPU Speed 2693 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Registers=26
  • Flip-Flops=26
MiscellaneousStatistics
  • AGG_BONDED_IO=17
  • AGG_IO=17
  • AGG_SLICE=29
  • NUM_4_INPUT_LUT=52
  • NUM_BONDED_IOB=17
  • NUM_BUFGMUX=1
  • NUM_CYMUX=25
  • NUM_LUT_RT=15
  • NUM_RAMB16=1
  • NUM_SLICEL=29
  • NUM_SLICE_FF=37
  • NUM_XOR=26
  • Xilinx Core dds_compiler_v4_0, Xilinx CORE Generator 14.7=1
NetStatistics
  • NumNets_Active=100
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=16
  • NumNodesOfType_Active_CLKPIN=26
  • NumNodesOfType_Active_CNTRLPIN=26
  • NumNodesOfType_Active_DOUBLE=112
  • NumNodesOfType_Active_DUMMY=117
  • NumNodesOfType_Active_DUMMYBANK=5
  • NumNodesOfType_Active_DUMMYESC=9
  • NumNodesOfType_Active_GLOBAL=8
  • NumNodesOfType_Active_HFULLHEX=1
  • NumNodesOfType_Active_HUNIHEX=20
  • NumNodesOfType_Active_INPUT=141
  • NumNodesOfType_Active_IOBOUTPUT=9
  • NumNodesOfType_Active_OMUX=49
  • NumNodesOfType_Active_OUTPUT=74
  • NumNodesOfType_Active_PREBXBY=29
  • NumNodesOfType_Active_VFULLHEX=5
  • NumNodesOfType_Active_VUNIHEX=19
  • NumNodesOfType_Gnd_BRAMADDR=5
  • NumNodesOfType_Gnd_CNTRLPIN=9
  • NumNodesOfType_Gnd_DOUBLE=6
  • NumNodesOfType_Gnd_DUMMYBANK=1
  • NumNodesOfType_Gnd_INPUT=1
  • NumNodesOfType_Gnd_OMUX=6
  • NumNodesOfType_Gnd_OUTPUT=2
  • NumNodesOfType_Gnd_PREBXBY=1
  • NumNodesOfType_Vcc_BRAMADDR=1
  • NumNodesOfType_Vcc_CNTRLPIN=4
  • NumNodesOfType_Vcc_VCCOUT=3
SiteStatistics
  • IOB-DIFFM=7
  • IOB-DIFFS=8
  • SLICEL-SLICEM=19
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IOB=17
  • IOB_INBUF=9
  • IOB_OUTBUF=8
  • IOB_PAD=17
  • RAMB16=1
  • RAMB16_RAMB16=1
  • RAMB16_RAMB16A=1
  • RAMB16_RAMB16B=1
  • SLICEL=29
  • SLICEL_CYMUXF=13
  • SLICEL_CYMUXG=12
  • SLICEL_F=23
  • SLICEL_F5MUX=1
  • SLICEL_FFX=16
  • SLICEL_FFY=21
  • SLICEL_G=29
  • SLICEL_XORF=13
  • SLICEL_XORG=13
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IOB
  • O1=[O1_INV:0] [O1:8]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:8]
IOB_PAD
  • DRIVEATTRBOX=[12:8]
  • IOATTRBOX=[LVCMOS25:17]
  • SLEW=[SLOW:8]
RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • SSRA=[SSRA_INV:0] [SSRA:1]
  • SSRB=[SSRB_INV:0] [SSRB:1]
  • WEA=[WEA:1] [WEA_INV:0]
  • WEB=[WEB:1] [WEB_INV:0]
RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • PORTA_ATTR=[2048X9:1]
  • SSRA=[SSRA_INV:0] [SSRA:1]
  • WEA=[WEA:1] [WEA_INV:0]
  • WRITEMODEA=[READ_FIRST:1]
RAMB16_RAMB16B
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • PORTB_ATTR=[2048X9:1]
  • SSRB=[SSRB_INV:0] [SSRB:1]
  • WEB=[WEB:1] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:1]
SLICEL
  • BX=[BX_INV:0] [BX:2]
  • BY=[BY:3] [BY_INV:0]
  • CIN=[CIN_INV:0] [CIN:12]
  • CLK=[CLK:24] [CLK_INV:0]
  • SR=[SR:10] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:13] [0_INV:0]
  • 1=[1_INV:0] [1:13]
SLICEL_CYMUXG
  • 0=[0:12] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:1] [S0_INV:0]
SLICEL_FFX
  • CK=[CK:16] [CK_INV:0]
  • D=[D:16] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:14] [INIT1:2]
  • FFX_SR_ATTR=[SRLOW:14] [SRHIGH:2]
  • LATCH_OR_FF=[FF:16]
  • SR=[SR:3] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:13] [SYNC:3]
SLICEL_FFY
  • CK=[CK:21] [CK_INV:0]
  • D=[D:21] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:18] [INIT1:3]
  • FFY_SR_ATTR=[SRLOW:18] [SRHIGH:3]
  • LATCH_OR_FF=[FF:21]
  • REV=[REV_INV:0] [REV:3]
  • SR=[SR:7] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:14] [SYNC:7]
SLICEL_XORF
  • 1=[1_INV:0] [1:13]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IOB
  • I=9
  • O1=8
  • PAD=17
IOB_INBUF
  • IN=9
  • OUT=9
IOB_OUTBUF
  • IN=8
  • OUT=8
IOB_PAD
  • PAD=17
RAMB16
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=1
  • CLKB=1
  • DOA0=1
  • DOA1=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • ENA=1
  • ENB=1
  • SSRA=1
  • SSRB=1
  • WEA=1
  • WEB=1
RAMB16_RAMB16
  • ADDRA=1
  • ADDRB=1
  • DIA=1
  • DIB=1
  • DOA=1
  • DOB=1
RAMB16_RAMB16A
  • ADDRA=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • CLKA=1
  • DIA=1
  • DOA=1
  • DOA0=1
  • DOA1=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • ENA=1
  • SSRA=1
  • WEA=1
RAMB16_RAMB16B
  • ADDRB=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKB=1
  • DIB=1
  • DOB=1
  • ENB=1
  • SSRB=1
  • WEB=1
SLICEL
  • BX=2
  • BY=3
  • CIN=12
  • CLK=24
  • COUT=12
  • F1=23
  • F2=16
  • F3=5
  • F4=2
  • G1=29
  • G2=21
  • G3=11
  • G4=9
  • SR=10
  • X=7
  • XQ=16
  • Y=9
  • YQ=21
SLICEL_CYMUXF
  • 0=13
  • 1=13
  • OUT=13
  • S0=13
SLICEL_CYMUXG
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
SLICEL_F
  • A1=23
  • A2=16
  • A3=5
  • A4=2
  • D=23
SLICEL_F5MUX
  • F=1
  • G=1
  • OUT=1
  • S0=1
SLICEL_FFX
  • CK=16
  • D=16
  • Q=16
  • SR=3
SLICEL_FFY
  • CK=21
  • D=21
  • Q=21
  • REV=3
  • SR=7
SLICEL_G
  • A1=29
  • A2=21
  • A3=11
  • A4=9
  • D=29
SLICEL_XORF
  • 0=13
  • 1=13
  • O=13
SLICEL_XORG
  • 0=13
  • 1=13
  • O=13
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 40 38 0 0 0 0 0
bitgen 13 13 0 0 0 0 0
map 28 28 0 0 0 0 0
netgen 1 1 0 0 0 0 0
ngc2edif 31 31 0 0 0 0 0
ngcbuild 4 4 0 0 0 0 0
ngdbuild 33 33 0 0 0 0 0
obngc 4 4 0 0 0 0 0
par 31 20 11 0 0 0 0
trce 19 19 0 0 0 0 0
xst 54 52 0 0 0 0 0
 
Help Statistics
Search words with results
command line ( 1 ) console ( 1 )
macro search ( 1 ) macro search path ( 1 )
Help files
/doc/usenglish/isehelp/dsm_p_using_message_filters_commandline.htm ( 1 ) /doc/usenglish/isehelp/ise_c_configuration_overview.htm ( 1 )
/doc/usenglish/isehelp/ise_c_using_fixed_netlist_ip.htm ( 1 ) /doc/usenglish/isehelp/ise_n_command_line_tools_user_guide.htm ( 1 )
/doc/usenglish/isehelp/ite_c_overview.htm ( 3 ) /doc/usenglish/isehelp/pim_t_command_line_conventions.htm ( 1 )
/doc/usenglish/isehelp/pn_c_using_console_error_warning_tabs.htm ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/SineSynth
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2013-12-15T23:29:22
PROP_intWbtProjectID=E5120F5DF98A43D6BAF31F998A21BD90 PROP_intWbtProjectIteration=20
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_selectedSimRootSourceNode_behav=work.SineSynth
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan3 PROP_DevDevice=xc3s1000
PROP_DevFamilyPMName=spartan3 PROP_DevPackage=ft256
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-5
PROP_PreferredLanguage=Verilog FILE_NGC=1
FILE_UCF=1 FILE_VERILOG=2
 
Core Statistics
Core Type=dds_compiler_v4_0
c_accumulator_width=26 c_amplitude=0 c_channels=1 c_has_ce=0
c_has_channel_index=0 c_has_phase_out=0 c_has_phasegen=1 c_has_rdy=0
c_has_rfd=0 c_has_sclr=0 c_has_sincos=1 c_latency=-1
c_mem_type=1 c_negative_cosine=0 c_negative_sine=0 c_noise_shaping=0
c_optimise_goal=0 c_output_width=8 c_outputs_required=0 c_phase_angle_width=8
c_phase_increment=3 c_phase_increment_value=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 c_phase_offset=0 c_phase_offset_value=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0
c_por_mode=0 c_use_dsp48=0 c_xdevicefamily=spartan3
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=28 NGDBUILD_NUM_FDR=2 NGDBUILD_NUM_FDRS=3
NGDBUILD_NUM_FDS=5 NGDBUILD_NUM_GND=2 NGDBUILD_NUM_IBUF=8 NGDBUILD_NUM_LUT2=36
NGDBUILD_NUM_LUT3=5 NGDBUILD_NUM_LUT4=11 NGDBUILD_NUM_MUXCY=26 NGDBUILD_NUM_MUXF5=1
NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=26
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=28 NGDBUILD_NUM_FDR=2 NGDBUILD_NUM_FDRS=3
NGDBUILD_NUM_FDS=5 NGDBUILD_NUM_GND=2 NGDBUILD_NUM_IBUF=8 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_LUT2=36 NGDBUILD_NUM_LUT3=5 NGDBUILD_NUM_LUT4=11 NGDBUILD_NUM_MUXCY=26
NGDBUILD_NUM_MUXF5=1 NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_RAMB16_S9_S9=1 NGDBUILD_NUM_TS_TIMESPEC=1
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=26
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s1000-5-ft256 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-verilog2001=YES -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -mult_style=Auto -iobuf=YES -max_fanout=100000
-bufg=8 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Yes -use_sync_set=Yes -use_sync_reset=Yes -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5