projects:fpga_piano
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projects:fpga_piano [2013/12/19 16:52] rdedhia [How can someone else build on it?] |
projects:fpga_piano [2013/12/19 21:36] (current) edorsky |
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| For our final project, we decided to program an FPGA to play simple music. We attempted to implement two different kinds of modes: a free-play mode where the user was able to play a combination of seven different notes in a major scale and a song mode where a predetermined song would play. In order to produce different notes, we divided the FPGA's clock by different values which yielded the various notes we wanted. We opted to use seven separate GPIO pins on the FPGA to produce notes, and we were able to play all the notes using a single speaker by building a simple analog signal adder. | For our final project, we decided to program an FPGA to play simple music. We attempted to implement two different kinds of modes: a free-play mode where the user was able to play a combination of seven different notes in a major scale and a song mode where a predetermined song would play. In order to produce different notes, we divided the FPGA's clock by different values which yielded the various notes we wanted. We opted to use seven separate GPIO pins on the FPGA to produce notes, and we were able to play all the notes using a single speaker by building a simple analog signal adder. | ||
| ==== Why did you do it? ==== | ==== Why did you do it? ==== | ||
| - | Throughout the semester, we have been working in Verilog, and wanted to see how this could be applied by programming an FPGA. We all like music and thought it would be cool to use user input to an FPGA to play chords and songs. In addition, we knew that we could generate signals for notes by dividing the clock of the FPGA, and this gave us an opportunity to have a relatively nicely scoped project. We were able to get code that played a single note fairly quickly, and were able to focus more efforts to learning about an FPGA. \linebreak | + | Throughout the semester, we have been working in Verilog, and wanted to see how this could be applied by programming an FPGA. We all like music and thought it would be cool to use user input to an FPGA to play chords and songs. In addition, we knew that we could generate signals for notes by dividing the clock of the FPGA, and this gave us an opportunity to have a relatively nicely scoped project. We were able to get code that played a single note fairly quickly, and were able to focus more efforts to learning about an FPGA. |
| There is a great deal that can be done with playing music, and with this project we could build our way up so we can have something working on every iteration. That way, we could continue adding new functionality to our project without worrying about not having something cool to show. | There is a great deal that can be done with playing music, and with this project we could build our way up so we can have something working on every iteration. That way, we could continue adding new functionality to our project without worrying about not having something cool to show. | ||
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| === FPGA === | === FPGA === | ||
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| + | An FPGA is a programmable circuit consisting of a large number of "logic cells." An individual logic cell contains a small lookup table, and may also contain an adder or another fundamental arithmetic circuit. "Programming" an FPGA involves setting the values of the lookup tables so that the FPGA produces the desired outputs for corresponding inputs. This means that few calculations are actually done on the FPGA -- rather the FPGA maps every input to the correct output. This lets FPGAs run at blazing speeds, far outpacing conventional processors depending on the task. As FPGAs have become more efficient and logic-dense, their applications have grown to a wide range of fields. | ||
| === Piano Mode === | === Piano Mode === | ||
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| In order to have all of our GPIO pins play their notes through the same speaker, we needed to construct a circuit that added the signals together. To accomplish this, we created a simple analog signal-adding circuit. This circuit uses an inverting amplifier to amplify the summed signal. | In order to have all of our GPIO pins play their notes through the same speaker, we needed to construct a circuit that added the signals together. To accomplish this, we created a simple analog signal-adding circuit. This circuit uses an inverting amplifier to amplify the summed signal. | ||
| - | The seven GPIO pins which generate the notes' frequencies are each attached to a 1kΩ resistor. These seven resistors are all attached to the noninverting input of the op amp. Note that the op amp pictured is not the one which we opted to use; while we used a TL081, it is fine to use most any op amp. | + | The seven GPIO pins which generate the notes' frequencies are each attached to a 1kΩ resistor. These seven resistors are all attached to the noninverting input of the op amp. Note that the op amp pictured is not the one which we opted to use; while we used a TL081, it is fine to use most any op amp. The inverting amplifier has a resistor, Rf, which determines the gain. |
| We also connect each GPIO pin to an LED, such that the LED's light up according to the note that we are playing. The notes we are playing are at a frequency high enough that the LED blinks too quickly to be visible to the human eye. As a result, it appears that the LED is always on for any note that is being played. | We also connect each GPIO pin to an LED, such that the LED's light up according to the note that we are playing. The notes we are playing are at a frequency high enough that the LED blinks too quickly to be visible to the human eye. As a result, it appears that the LED is always on for any note that is being played. | ||
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| === Difficulties === | === Difficulties === | ||
| - | Our main diculty was in implementing the music code (i.e., the module that played a simple song). We managed to synthesize the master.v module and its dependent modules in the Xilinx ISE, but whenever we attempted to confi gure the target device, we got an un-logged error which prevented us from compiling the code onto the FPGA. | + | Our main difficulty was in implementing the music code (i.e., the module that played a simple song). We managed to synthesize the master.v module and its dependent modules in the Xilinx ISE, but whenever we attempted to confi gure the target device, we got an un-logged error which prevented us from compiling the code onto the FPGA. The problem is likely to lie in the intricacies of FPGA programming best practices, and we didn't have time to debug it. |
| === Future Work === | === Future Work === | ||
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| === Code Appendix === | === Code Appendix === | ||
| - | All of our code is in our github repository: https://github.com/mdelrosa/cafinalproject. The ucf files are all responsible for mapping between the FPGA and our verilog code. The relevant code with regard to the user input piano is in piano.ucf, and piano.v, and the code with regard to playing music with a look up table is in music_code.ucf, LUT_song.v, and memory.mem. The code responsible for switching between the modes is in master.ucf and master.v. | + | All of our code is in our github repository: https://github.com/mdelrosa/cafinalproject. The ucf files are all responsible for mapping between the FPGA and our verilog code. The relevant code with regard to the user input piano is in piano.ucf and piano.v, and the code with regard to playing music with a look up table is in master.ucf, LUT_song.v, and memory.mem. The code responsible for switching between the modes and interacting with the FPGA is in master.v. |
projects/fpga_piano.1387489936.txt.gz · Last modified: 2013/12/19 16:52 by rdedhia
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