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projects:fpga_piano [2013/12/19 21:20] mdelrosa [How Did You Do It?] |
projects:fpga_piano [2013/12/19 21:36] (current) edorsky |
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=== Difficulties === | === Difficulties === | ||
- | Our main difficulty was in implementing the music code (i.e., the module that played a simple song). We managed to synthesize the master.v module and its dependent modules in the Xilinx ISE, but whenever we attempted to configure the target device, we got an un-logged error which prevented us from compiling the code onto the FPGA. | + | Our main difficulty was in implementing the music code (i.e., the module that played a simple song). We managed to synthesize the master.v module and its dependent modules in the Xilinx ISE, but whenever we attempted to configure the target device, we got an un-logged error which prevented us from compiling the code onto the FPGA. The problem is likely to lie in the intricacies of FPGA programming best practices, and we didn't have time to debug it. |
=== Future Work === | === Future Work === | ||
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=== Code Appendix === | === Code Appendix === | ||
- | All of our code is in our github repository: https://github.com/mdelrosa/cafinalproject. The ucf files are all responsible for mapping between the FPGA and our verilog code. The relevant code with regard to the user input piano is in piano.ucf, and piano.v, and the code with regard to playing music with a look up table is in music_code.ucf, LUT_song.v, and memory.mem. The code responsible for switching between the modes is in master.ucf and master.v. | + | All of our code is in our github repository: https://github.com/mdelrosa/cafinalproject. The ucf files are all responsible for mapping between the FPGA and our verilog code. The relevant code with regard to the user input piano is in piano.ucf and piano.v, and the code with regard to playing music with a look up table is in master.ucf, LUT_song.v, and memory.mem. The code responsible for switching between the modes and interacting with the FPGA is in master.v. |