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====== FPGA Piano ======
Made by: Mason del Rosario, Evan Dorsky, Rahil Dedhia, Jamie Gorson, Jack Fan
====  What did you do?  ====
For our final project, we decided to program an FPGA to play simple music. We attempted to implement two different kinds of modes: a free-play mode where the user was able to play a combination of seven different notes in a major scale and a song mode where a predetermined song would play. In order to produce different notes, we divided the FPGA's clock by different values which yielded the various notes we wanted. We opted to use seven separate GPIO pins on the FPGA to produce notes, and we were able to play all the notes using a single speaker by building a simple analog signal adder.

=== Piano Mode ===

One mode in which our FPGA can operate is a free play mode. In this mode, we utilize seven of the eight switches on our FPGA as user input. We use piano.ucf to map these switches as an input to the piano.v file, which then utilizes them to determine the signals that are sent to seven GPIO pins on the FPGA. This is by dividing the clock of the FPGA in order to create seven different signals with the frequencies necessary to play the notes we wanted. Using the FPGA, we can have a 25MHz, 50Mhz, or 100Mhz clock, so despite only having seven pins to play different notes, we can have three full octaves of music by switching the clock.

=== Music with a LUT ===

The other mode in which want our FPGA to operate is to play a predetermined song. We wrote verilog code to do this, and while this code synthesizes correctly, we are unable to make it work on the FPGA for presently unknown reasons. The code that does this is in LUT\_song.v, which uses a look up table to read from a mem file that contains instructions for individual notes in the form of seven bit binary strings to denote the seven notes that are mapped to our GPIO pins on the FPGA. Currently, the look up table reads from the master.mem file in the appendix, and uses a frequency divider to play each note of We Wish You a Merry Christmas for about a second long.
====  Why did you do it?  ====
Throughout the semester, we have been working in Verilog, and wanted to see how this could be applied by programming an FPGA. We all like music and thought it would be cool to use user input to an FPGA to play chords and songs. In addition, we knew that we could generate signals for notes by dividing the clock of the FPGA, and this gave us an opportunity to have a relatively nicely scoped project. We were able to get code that played a single note fairly quickly, and were able to focus more efforts to learning about an FPGA. \linebreak

There is a great deal that can be done with playing music, and with this project we could build our way up so we can have something working on every iteration. That way, we could continue adding new functionality to our project without worrying about not having something cool to show.
.====  How did you do it?  ====
This portion can assume an audience that has taken Computer Architecture, but don’t get burdened by
buzzwords. A sure sign of a bad engineer is over reliance on acroynms.
====  How can someone else build on it?  ====
Include everything necessary to pick up where you left off.
This should include:
  * Code
  * Schematics
  * build instructions
  * A list of difficulties and ‘gotchas’ while doing this project
  * Work Plan reflection
  * A possible TODO to extend the depth of the project

=== Build Instructions: Quickstart ===

1. Download Xilinx ISE design tools at http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html. 

2. Clone github repo: https://github.com/mdelrosa/cafinalproject

3. Create a new project in Xilinx (follow instructions from http://tinyurl.com/ca-fpga-13; these next steps outline the process described in the tutorial)

4. Add piano.v as a source

5. Right click on piano.v, click on add source, and add piano.ucf

6. Click on the Green arrow that says "Implement Top Module"; this should synthesize your top level module and implement the design constraints set by the ucf file

7. Double click on "Configure Target Device"

8. Make sure your FPGA is attached to your computer and click on the Boundary Scan button

9. Click on initialize chain; select the .bit file that was generated during synthesis on the first menu that pops up, then click bypass on the second menu

10. Program the chip on the left by right clicking on it and hitting program.

11. If you have not already, build the circuit found in the Analog Circuit subsection. Ensure that the appropriate GPIO pins are attached since the UCF file denotes these specific pins from the FPGA.

12. Use the switches to play different notes/combinations of notes.

=== Analog Circuit ===

In order to have all of our GPIO pins play their notes through the same speaker, we needed to construct a circuit that added the signals together. To accomplish this, we created a simple analog signal-adding circuit. This circuit uses an inverting amplifier to amplify the summed signal.

The seven GPIO pins which generate the notes' frequencies are each attached to a 1kΩ resistor. These seven resistors are all attached to the noninverting input of the op amp. Note that the op amp pictured is not the one which we opted to use; while we used a TL081, it is fine to use most any op amp.

{{ wiki:signaladder.png?400 }}

This should all be in zip file(s) on your wiki page.
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