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2014:labview_visualizations [2014/12/27 17:31]
guthrie
2014:labview_visualizations [2015/01/02 10:16] (current)
guthrie
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 We used clusters like nets in verilog. We used a shift register as a program counter and had three different operations we could do: math, store, and load. We used case statements as muxes and only used gates to construct most of this. We used clusters like nets in verilog. We used a shift register as a program counter and had three different operations we could do: math, store, and load. We used case statements as muxes and only used gates to construct most of this.
 {{:​2014:​cpu.png|}} {{:​2014:​cpu.png|}}
 +
 We started this project by constructing a half adder. As you can see all the logic is done with gates instead of using LabView’s math tools. ​ We started this project by constructing a half adder. As you can see all the logic is done with gates instead of using LabView’s math tools. ​
 {{:​2014:​halfadder.png|}} {{:​2014:​halfadder.png|}}
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 {{:​2014:​instructionfetch.png|}} {{:​2014:​instructionfetch.png|}}
 This unit introduced us to a few of the drawbacks we found. The first is that case statements as we used them to represent Mux's don't quite visually represent the process of using an address to select from many inputs. The process of constructing the mux equivalent involved hooking up each input to the output when the case state was that inputs address. This process could be avoided if people were provided with a library of muxs with different input numbers, but that too seemed a little weird. ​ This unit introduced us to a few of the drawbacks we found. The first is that case statements as we used them to represent Mux's don't quite visually represent the process of using an address to select from many inputs. The process of constructing the mux equivalent involved hooking up each input to the output when the case state was that inputs address. This process could be avoided if people were provided with a library of muxs with different input numbers, but that too seemed a little weird. ​
 +{{ :​2014:​regfile.png |}}
 This is our memory file. We used an addition operator as well as branch statements in order to change things from binary into numbers so it would be easy to wire up our muxes. Other than this nothing from the math pallet was used in our CPU. We used global variables to represent our registers, though we later learned this was wrong. If we were going to redo this, we would use shift registers instead. Our register file was very similar to this except it only had 2 cases and outputted both registers.  ​ This is our memory file. We used an addition operator as well as branch statements in order to change things from binary into numbers so it would be easy to wire up our muxes. Other than this nothing from the math pallet was used in our CPU. We used global variables to represent our registers, though we later learned this was wrong. If we were going to redo this, we would use shift registers instead. Our register file was very similar to this except it only had 2 cases and outputted both registers.  ​
  
- +**How you can help** 
 +The project can be extended by testing the vi's with more people of varying levels of LabView experience. Our VI's included in the zip folder, could be built upon and revised into a partially completed state for exercises. Also in the zip folder is the writeup of what components are comparable to what so that you could make a set of vi's yourself. By either using and documenting your experience with the VIs or building your own you could help further test the usability of LabView as a teaching tool. 
 +{{:​2014:​finalproject.7z|}}
2014/labview_visualizations.1419719484.txt.gz · Last modified: 2014/12/27 17:31 by guthrie