projects:binary_clock
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projects:binary_clock [2013/12/19 22:00] phiaseitz [Gotchas] |
projects:binary_clock [2013/12/19 23:38] (current) eqwang [**Code**] |
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| - | **Binary Clock** | + | ==================Binary Clock================== |
| by Emily Wang ('16) and Sophia Seitz ('16) | by Emily Wang ('16) and Sophia Seitz ('16) | ||
| - | ====== What did you do? ====== | + | Computer Architecture, Fall 2013 |
| + | ====== What did we do? ====== | ||
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| - | ====== Why did you do it? ====== | + | ====== Why did we do it? ====== |
| + | We knew that we wanted more experience with the FPGA beyond the MP3 lab option. Most of our exposure with programming in Computer Architecture has been with Verilog simulations in ModelSim or MARS Assembly, which is obviously different from uploading to and debugging code running on the FPGA (for example, frequency dividers in structural with flip flops work fine in ModelSim, but caused unexpected troubles on the FPGA). Therefore, we chose to run our Verilog code on an FPGA to help create the binary clock in real life. | ||
| + | Also, we wanted to pursue a project that could be used to help teach others about Computer Architecture topics, such as binary numbers, multiplexers, adders, and frequency dividers, which are all essential pieces of our binary clock. | ||
| - | We also knew that we wanted more experience with the FPGA beyond the MP3 lab option and also wanted a project that could be used to help teach others about Computer Architecture topics, such as binary numbers, multiplexers, adders, and frequency dividers, which are all essential pieces of our binary clock. | + | ====== How did we do it? ====== |
| - | + | ||
| - | ====== How did you do it? ====== | + | |
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| - | ==== **Code** ==== | + | ====Code==== |
| + | |||
| + | The current code for this project can be found at **https://github.com/greenteawarrior/BinaryClock** | ||
| - | The current code for this project can be found at https://github.com/greenteawarrior/BinaryClock. | ||
| Feel free to fork this repository and play with the binary clock! Also, let us know if you do anything interesting. :) | Feel free to fork this repository and play with the binary clock! Also, let us know if you do anything interesting. :) | ||
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| For our project, we built an case for our clock. We did this by laser cutting 3/16 inch MDF, and then gluing the case together. The CAD for the casing and a rudimentary CAD of our FPGA, the Spartan 3, can be found here: | For our project, we built an case for our clock. We did this by laser cutting 3/16 inch MDF, and then gluing the case together. The CAD for the casing and a rudimentary CAD of our FPGA, the Spartan 3, can be found here: | ||
| - | INSERT CAD FILES HERE! | + | *The github repository (includes code and CAD) can also be very easily downloaded as a .zip file if that is preferred. Please email Emily Wang or Sophia Seitz if you have any technical difficulties with obtaining the open source files. Thanks!* |
| - | Here is a picture of the finished product! | + | We have a folder of the CAD files involved in creating the binary clock on the github repository : https://github.com/greenteawarrior/BinaryClock/tree/master/CAD |
| - | INSERT PICTURE HERE! | + | (Tolerances calibrated for cutting with a Trotec Speedy300 laser cutter - as always, prototype the LED diameter tolerances to prevent excessive filing/post-processing!). |
| + | |||
| + | Some screenshots of the assembly in SolidWorks: | ||
| + | {{ :projects:binaryclock_casingfront.png?500 |}} | ||
| + | {{ :projects:binaryclock_casingback.png?500 |}} | ||
| + | |||
| + | Here is a picture of the finished product! | ||
| + | {{ :projects:binaryclockfinalpicture.jpg?500 |}} | ||
| ==== Gotchas ==== | ==== Gotchas ==== | ||
| - | * For some reason, the FPGA does not play well with frequency dividers implemented in structural verilog (i.e. lots of flip flops) when you're trying to display something tied directly to the clock signal. We still aren't sure exactly why this happens, but writing one big frequency divider in behavioral verilog seems to work well enough. This may involve exploring with the Digital Clock Manager, but it did not seem appropriate for the ultimate 2Hz frequency we desired. There's one warning message, which can, as far as we can tell, be ignored. The clock still works, and seems pretty accurate. | + | * For some reason, the FPGA does not play well with frequency dividers implemented in structural verilog (i.e. lots of flip flops) when you're trying to display something tied directly to the clock signal. We still aren't sure exactly why this happens, but writing one big frequency divider in behavioral verilog seems to work well enough. This may involve exploring with the Digital Clock Manager feature in the Xilinx software, but it did not seem appropriate for the ultimate 2Hz frequency we desired. There's one warning message, which can, as far as we can tell, be ignored. The clock still works, and seems pretty accurate. |
| * When writing the .ucf file, be sure to check where your outputs and inputs map. The switches and pins 7 -14 on header J8 map to the same place, so you can use only one or the other. | * When writing the .ucf file, be sure to check where your outputs and inputs map. The switches and pins 7 -14 on header J8 map to the same place, so you can use only one or the other. | ||
| * If you're set on the color of the LEDs, and want to have a specific one, make sure they work. We tried to make our clock have orange LEDs, using some RGB LEDs. They appeared to work when we turned the FPGA on, but when we started running our code, they turned greenish. We think this is because the FPGA outputs a different voltage when it is on, as opposed to when it is running a program. | * If you're set on the color of the LEDs, and want to have a specific one, make sure they work. We tried to make our clock have orange LEDs, using some RGB LEDs. They appeared to work when we turned the FPGA on, but when we started running our code, they turned greenish. We think this is because the FPGA outputs a different voltage when it is on, as opposed to when it is running a program. | ||
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| ===== Possible Future Steps ===== | ===== Possible Future Steps ===== | ||
| - | * Make the LEDs actually orange | + | * Make the LEDs actually orange (This was Sophia's intended color for the display LEDs.) |
| - | * Add color changing LEDs! | + | * Add color changing LED pattern logic! (Rainbows, anyone?) |
| * The clock is fairly accurate, but does get off by a few seconds every couple hours. The frequency dividers could use some fine-tuning. | * The clock is fairly accurate, but does get off by a few seconds every couple hours. The frequency dividers could use some fine-tuning. | ||
| * Add some code to prevent the user from setting minutes or seconds to values above 60. (same concept for setting hours above 24) | * Add some code to prevent the user from setting minutes or seconds to values above 60. (same concept for setting hours above 24) | ||
| - | * Make a PCB instead of the sketchy breadboard wiring we currently have. | + | * Make a PCB instead of the breadboard wiring we currently have. |
| - | * In addition to a time, we could also have the clock display date. | + | * In addition to the time values, we could also have the clock display date (day of the week, year, etc). |
projects/binary_clock.1387508400.txt.gz · Last modified: 2013/12/19 22:00 (external edit)
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