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        <dc:date>2013-12-20T14:49:29-04:00</dc:date>
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        <description>FIXME Not enough cats.

Some Assembly Required

Comp Arch Fall 2013 final project

[Is Assembly Required: Yes]








Team: Charles Goddard (2015), Victoria Coleman (2015), Eric Tappan (2015)

What We Did

We created an autonomous robot that explores the world in linear trajectories while avoiding obstacle using IR range-finding.</description>
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    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:binary_clock&amp;rev=1387514327&amp;do=diff">
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        <dc:date>2013-12-19T23:38:47-04:00</dc:date>
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        <link>https://wikis.olin.edu/ca/doku.php?id=projects:binary_clock&amp;rev=1387514327&amp;do=diff</link>
        <description>Binary Clock

by Emily Wang ('16) and Sophia Seitz ('16)

Computer Architecture, Fall 2013

What did we do?

For our Computer Architecture final project, we made a clock that tells the time in binary using Verilog, a Spartan 3 FPGA, and some LEDS. Quite spiffy indeed.</description>
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        <dc:date>2013-12-19T23:19:37-04:00</dc:date>
        <title>projects:cordic_algorithm</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:cordic_algorithm&amp;rev=1387513177&amp;do=diff</link>
        <description>CORDIC Implementation

Made by: Claire Barnes

What did you do?

For my final project, I decided to implement the CORDIC algorithm in Verilog. The CORDIC algorithm implements trigonometric, hyperbolic, and logarithmic functions in digital logic using only bit-shifts, additions (and subtractions), and one look up table. I was only able to implement the sine and cosine functions. My reach goal was to implement log in any base, but I did not have time. So I focused on sine and cosine and creating a…</description>
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        <dc:date>2013-12-19T23:35:57-04:00</dc:date>
        <title>projects:cpu_display</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:cpu_display&amp;rev=1387514157&amp;do=diff</link>
        <description>Central Processing Unit

a display of not-so-black boxes

By: Lyra Silverwolf



What I Did

I built a display/diorama of an entire computer Central Processing Unit (CPU) out of nested cardboard boxes.

At the highest level of abstraction are the 5 major information stages a CPU is commonly divided into: instruction fetching, instruction decoding, the register file, the arithmetic logic unit (ALU), and data memory. I chose these particular stages for the CPU, because in a pipeline CPU when multi…</description>
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        <dc:date>2013-12-15T17:08:05-04:00</dc:date>
        <title>projects:example</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:example&amp;rev=1387145285&amp;do=diff</link>
        <description>This is an example project page for a project that doesn't exist. You can make your own (for projects that do exist) by creating a link ([[projects:My_project|creating a link]]) then using the edit option on the resulting article. Neato.

You can look at the source for this page using the edit button over there somewhere</description>
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    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:fibre-optic_video_transmission_for_aircraft_implementation&amp;rev=1387341132&amp;do=diff">
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        <dc:date>2013-12-17T23:32:12-04:00</dc:date>
        <title>projects:fibre-optic_video_transmission_for_aircraft_implementation</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:fibre-optic_video_transmission_for_aircraft_implementation&amp;rev=1387341132&amp;do=diff</link>
        <description>Fibre Optic Video Transmission for Aircraft: Implementation

By Steven Cooreman

What did you do?

I made a blazing fast video signal converter in VHDL.

Traditionally, transmission of critical video signals in aircraft has been done as an analog signal over copper coaxial cable. However, as manufacturers look for new ways to reduce the take-off weight of aircraft, the focus has been shifted to Plastic Optical Fiber (POF). This requires a new protocol to transmit video, because optical fiber can…</description>
    </item>
    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:fpga_note_generator&amp;rev=1388446065&amp;do=diff">
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        <dc:date>2013-12-30T18:27:45-04:00</dc:date>
        <title>projects:fpga_note_generator</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:fpga_note_generator&amp;rev=1388446065&amp;do=diff</link>
        <description>FPGA Note Generator

by Caitlin Riley

What I Did

[Note Generator]

I turned my FPGA into an instrument capable of playing eight notes. The eight switches on the FPGA are set to correspond to a note in an A natural minor scale. When a switch is on, the FPGA outputs an 8-bit quantized sine wave corresponding to that note. The sine wave is then converted into an analog signal that drives a speaker. A video of it working can be downloaded</description>
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        <dc:date>2013-12-19T21:36:14-04:00</dc:date>
        <title>projects:fpga_piano</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:fpga_piano&amp;rev=1387506974&amp;do=diff</link>
        <description>FPGA Piano

Made by: Mason del Rosario, Evan Dorsky, Rahil Dedhia, Jamie Gorson, Jack Fan

What did you do?

For our final project, we decided to program an FPGA to play simple music. We attempted to implement two different kinds of modes: a free-play mode where the user was able to play a combination of seven different notes in a major scale and a song mode where a predetermined song would play. In order to produce different notes, we divided the FPGA's clock by different values which yielded t…</description>
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        <dc:format>text/html</dc:format>
        <dc:date>2013-12-19T10:21:32-04:00</dc:date>
        <title>projects:fpga_tuner</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:fpga_tuner&amp;rev=1387466492&amp;do=diff</link>
        <description>FPGA Tuner

by Claire Keum, Lisa Ventura

Here's a link to our website:
Computer Architecture FA13 FPGA Tuner

Final Report is included in the website.

If you have any questions, feel free to send me an email: &lt;ayoung.keum@students.olin.edu&gt;&lt;lventura@wellesley.edu&gt;</description>
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    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:gpu_cpu_feed_forward_neural_net&amp;rev=1389559183&amp;do=diff">
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        <dc:date>2014-01-12T15:39:43-04:00</dc:date>
        <title>projects:gpu_cpu_feed_forward_neural_net</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:gpu_cpu_feed_forward_neural_net&amp;rev=1389559183&amp;do=diff</link>
        <description>GPU / CPU feed forward neural net implementation

Link to github of project:

&lt;https://github.com/lukemetz/Neural-Net-Experiments&gt;

Drop me a email at: luke.s.metz&lt;&lt;at&gt;&gt;gmail&lt;dot&gt;com if you have questions or comments!</description>
    </item>
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        <dc:date>2013-12-19T22:19:24-04:00</dc:date>
        <title>projects:gpu_exploration</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:gpu_exploration&amp;rev=1387509564&amp;do=diff</link>
        <description>GPU Exploration: : A Learn and Teach Final Project

By Chloe Eghtebas

Note: I took advantage of the write up being on the wiki. Each link embedded in the text is a part of my write up so be sure to click on them all! Click on  my documentation to start! 

What I did</description>
    </item>
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        <dc:format>text/html</dc:format>
        <dc:date>2013-12-18T19:45:54-04:00</dc:date>
        <title>projects:latent_dirichlet_allocation</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:latent_dirichlet_allocation&amp;rev=1387413954&amp;do=diff</link>
        <description>Example</description>
    </item>
    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:logic_blox&amp;rev=1387432928&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2013-12-19T01:02:08-04:00</dc:date>
        <title>projects:logic_blox</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:logic_blox&amp;rev=1387432928&amp;do=diff</link>
        <description>LOGIC BLOX

----------

Sorry for the bare-bones wiki page. Check out the writeup. I promise it's not dry and boring. Also, you'll learn how to make your own Logic Blox from the files provided. They're really pretty!

----------



----------
   Mid-project slideshow presentation.</description>
    </item>
    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:matrix_multiplier&amp;rev=1387547726&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2013-12-20T08:55:26-04:00</dc:date>
        <title>projects:matrix_multiplier</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:matrix_multiplier&amp;rev=1387547726&amp;do=diff</link>
        <description>Matrix Multiplier

 Gredelston and Jangowitz 

What did we do?

Matrix multipliers!! We created a hardware implementation for a matrix multiplier, and also implemented the multiplier in assembly. In this particular case, we limited our multiplier to</description>
    </item>
    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:mechanical_logic_from_common_materials&amp;rev=1387416588&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2013-12-18T20:29:48-04:00</dc:date>
        <title>projects:mechanical_logic_from_common_materials</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:mechanical_logic_from_common_materials&amp;rev=1387416588&amp;do=diff</link>
        <description>Abstract

For our Computer Architecture final, we (Chris Joyce and Brendan Ritter) created mechanical logic gates as part of a lesson plan on computers for middle-school aged children.  Detailed instructions on how to build the gates described in this document can be found at the bottom of the page.</description>
    </item>
    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:optimization_of_a_pipelined_cpu&amp;rev=1387516994&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2013-12-20T00:23:14-04:00</dc:date>
        <title>projects:optimization_of_a_pipelined_cpu</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:optimization_of_a_pipelined_cpu&amp;rev=1387516994&amp;do=diff</link>
        <description>Optimizing a Pipelined CPU

Brendan Caporaletti, Chelsea Bailey, Jeffrey Hanford

Code: &lt;https://www.dropbox.com/s/2ulskrgce5xltpq/CPU_ResourceFiles.zip&gt;

The Vision

We made an optimized, 32-bit Pipelined CPU with features including: hazard avoidance, branch prediction, and MIPS compliance.

We began by creating a working 32-bit CPU with static branch prediction and data forwarding that was not quite compliant with MIPS architecture. The goal of this project was to use that CPU as a base for ex…</description>
    </item>
    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:pipelined_cpu_hazards_eliminated&amp;rev=1387428221&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2013-12-18T23:43:41-04:00</dc:date>
        <title>projects:pipelined_cpu_hazards_eliminated</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:pipelined_cpu_hazards_eliminated&amp;rev=1387428221&amp;do=diff</link>
        <description>Pipelined CPU, hazards eliminated

By Shivam Desai, Kris Groth, Sarah Strohkorb, Eric Westman

What did you do?

We used this project as an opportunity to model and simulate a pipelined CPU.

Pipelining a CPU increases efficiency significantly by dividing up the different functional chunks of the processor and assigning a different task to each one. There are five such functional stages in our processor: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory (MEM), and Writeback (…</description>
    </item>
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        <dc:date>2014-01-12T15:36:26-04:00</dc:date>
        <title>projects:projects</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:projects&amp;rev=1389558986&amp;do=diff</link>
        <description>Stuff must be here soon. For previous years, please reference ca.olin.edu.

Example

----------

 Assembly Car

 Binary Clock

 CORDIC Algorithm

CPU Display

Fibre-optic video transmission for aircraft implementation

 FPGA Note Generator

 FPGA Piano

 FPGA Tuner

 GPU Exploration

 GPU/CPU Feed Forward Neural Net

 Latent Dirichlet Allocation

Logic Blox

Matrix Multiplier

 Mechanical Logic From Common Materials

 Optimization of a Pipelined CPU

 Pipelined CPU, hazards eliminated

 RFID Exp…</description>
    </item>
    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:rfid_exploration&amp;rev=1387494176&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2013-12-19T18:02:56-04:00</dc:date>
        <title>projects:rfid_exploration</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:rfid_exploration&amp;rev=1387494176&amp;do=diff</link>
        <description>RFID Exploration

Louis Yi, Mary Ruthven, Kevin O'Toole, &amp; Jay Patterson

What did you do?

We made an Radio Frequency ID (RFID) card reader and, while attempting to create a long-range spoofer, created an jammer which overcomes card's signals.

The reader uses filtering circuitry following a 125kHz driven resonator to produce the returned FSK signal from the HID brand RFID proximity cards used around Olin college. Reading was initially performed by capturing data with an oscilloscope and then p…</description>
    </item>
    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:snap_circuits&amp;rev=1387550616&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2013-12-20T09:43:36-04:00</dc:date>
        <title>projects:snap_circuits</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:snap_circuits&amp;rev=1387550616&amp;do=diff</link>
        <description>Snap Circuits

For questions, please contact Nicole.Rifkin@students.olin.edu or Mitchell.Cieminski@students.olin.edu

LOGIC GATES:

Logic gates take in some number of inputs, where each input is a binary value: a true input is represented with a 1, and means that some voltage is supplied. A false input is represented with a 0, and means that there is no voltage supplied. Logic gates always have an output that is dependent on the inputs.
A logic gate’s behavior is represented with a truth table, …</description>
    </item>
    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:sorting_algorithms_in_assembly&amp;rev=1387482944&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2013-12-19T14:55:44-04:00</dc:date>
        <title>projects:sorting_algorithms_in_assembly</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:sorting_algorithms_in_assembly&amp;rev=1387482944&amp;do=diff</link>
        <description>Here is the link to the super duper fancy website for the project: 

&lt;http://sortingalgorithmsinassembly.weebly.com/&gt;

Please feel free to send any questions to thomas.nattestad@students.olin.edu</description>
    </item>
    <item rdf:about="https://wikis.olin.edu/ca/doku.php?id=projects:unicycle_lights&amp;rev=1388765771&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2014-01-03T11:16:11-04:00</dc:date>
        <title>projects:unicycle_lights</title>
        <link>https://wikis.olin.edu/ca/doku.php?id=projects:unicycle_lights&amp;rev=1388765771&amp;do=diff</link>
        <description>Unicycle Lights

Computer Architecture, Fall 2013

Heather Boortz

----------

What

I made unicycle lights using an FPGA. I made several different patterns of lights, and wrote the code such that it is easy for other users to add their own patterns. The switches on the FPGA board choose the pattern. Both the LEDs on the FPGA board as well as external LEDS can be controlled. A video can be viewed here:</description>
    </item>
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