module vgaTop(clk,red,green,blue,hsync,vsync);
input clk; 
output wire [7:0] red,green,blue;
output wire vsync, hsync;

wire hi, vi, dnc;
wire [7:0] redi, greeni, bluei;

ClkDivider pixelClk(clk, pclk);
vga display(pclk,dnc,hi,vi,redi,greeni,bluei);
assign red = redi;
assign green = greeni;
assign blue = bluei;
assign vsync = vi;
assign hsync = hi;
endmodule

module Top(clk,Red,Green,Blue,HS,VS);
input clk;
output [7:0] Red, Green, Blue;
output HS, VS;

wire hi, vi, dnc;
wire [7:0] redi, greeni, bluei;

vgaTop vga(clk, redi,greeni,bluei, hi, vi);
assign Red = redi;
assign Blue = bluei;
assign Green = greeni;
assign VS = vi;
assign HS = hi;
endmodule
