testMem Project Status (12/17/2014 - 15:53:26)
Project File: | Final.xise | Parser Errors: | No Errors
Module Name: | Top | Implementation State: | Synthesized
Target Device: | xc3s1000-5ft256 | Errors: | No Errors
Product Version: | ISE 14.7 | Warnings: | 5 Warnings (0 new)
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: |

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slices | 93 | 7680 | 1%
Number of Slice Flip Flops | 40 | 15360 | 0%
Number of 4 input LUTs | 168 | 15360 | 1%
Number of bonded IOBs | 27 | 173 | 15%
Number of GCLKs | 2 | 8 | 25%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Wed Dec 17 15:53:25 2014 | 0 | 5 Warnings (0 new) | 2 Infos (0 new)
Translation Report | Out of Date | Wed Dec 17 15:32:28 2014 | 0 | 0 | 0
Map Report | Out of Date | Wed Dec 17 15:32:38 2014 | 0 | 0 | 2 Infos (2 new)
Place and Route Report | Out of Date | Wed Dec 17 15:32:50 2014 | 0 | 0 | 2 Infos (2 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Out of Date | Wed Dec 17 15:32:53 2014 | 0 | 0 | 6 Infos (6 new)
Bitgen Report | Out of Date | Wed Dec 17 15:32:58 2014 | 0 | 0 | 1 Info (1 new)

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Out of Date | Wed Dec 17 15:32:58 2014
WebTalk Log File | Out of Date | Wed Dec 17 15:33:22 2014

Date Generated: 12/17/2014 - 15:53:26