module vga640x480(
                input wire dclk,                                 //pixel clock: 25MHz
                input wire clr,                                    //asynchronous reset
                output wire hsync,                          //horizontal sync out
                output wire vsync,                          //vertical sync out
                output reg  red,       //red vga output
                output reg  green, //green vga output
                output reg  blue      //blue vga output
                );

// video structure constants
parameter hpixels = 800;// horizontal pixels per line
parameter vlines = 521; // vertical lines per frame
parameter hpulse = 96;                 // hsync pulse length
parameter vpulse = 2;    // vsync pulse length
parameter hbp = 144;    // end of horizontal back porch
parameter hfp = 784;     // beginning of horizontal front porch
parameter vbp = 31;                       // end of vertical back porch
parameter vfp = 511;      // beginning of vertical front porch
// active horizontal video is therefore: 784 - 144 = 640
// active vertical video is therefore: 511 - 31 = 480

// registers for storing the horizontal & vertical counters
reg [9:0] hc;
reg [9:0] vc;

// Horizontal & vertical counters --
// this is how we keep track of where we are on the screen.
// ------------------------
// Sequential "always block", which is a block that is
// only triggered on signal transitions or "edges".
// posedge = rising edge  &  negedge = falling edge
// Assignment statements can only be used on type "reg" and need to be of the "non-blocking" type: <=
always @(posedge dclk or posedge clr)
begin
                // reset condition
                if (clr == 1)
                begin
                                hc <= 0;
                                vc <= 0;
                end
                else
                begin
                                // keep counting until the end of the line
                                if (hc < hpixels - 1)
                                                hc <= hc + 1;
                                else
                                // When we hit the end of the line, reset the horizontal
                                // counter and increment the vertical counter.
                                // If vertical counter is at the end of the frame, then
                                // reset that one too.
                                begin
                                                hc <= 0;
                                                if (vc < vlines - 1)
                                                                vc <= vc + 1;
                                                else
                                                                vc <= 0;
                                end
                                
                end
end

// generate sync pulses (active low)
// ----------------
// "assign" statements are a quick way to
// give values to variables of type: wire
assign hsync = (hc < hpulse) ? 0:1;
assign vsync = (vc < vpulse) ? 0:1;

// display 100% saturation colorbars
// ------------------------
// Combinational "always block", which is a block that is
// triggered when anything in the "sensitivity list" changes.
// The asterisk implies that everything that is capable of triggering the block
// is automatically included in the sensitivty list.  In this case, it would be
// equivalent to the following: always @(hc, vc)
// Assignment statements can only be used on type "reg" and should be of the "blocking" type: =
always @(*)
begin
        red<= 1;
        blue<= 1;
        green<= 1;
end
endmodule


module vgaTop(clk,red,green,blue,hsync,vsync);
input clk; 
output wire red,green,blue;
output wire vsync, hsync;
wire pclk;
wire dnc = 0;

ClkDivider pixelClk(clk, pclk);
vga640x480 display(pclk,dnc,hsync,vsync,red,green,blue);

endmodule

module ActualTop(clk,Red,Green,Blue,HS,VS);
input clk;
output Red, Green, Blue;
output HS, VS;

vgaTop vga(clk, Red,Green,Blue, HS, VS);

endmodule