Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s1000
Project ID (random number) 9420f6f36f0143a08d15315a9cec1ff2.1BF1B53EA1BD4DB3BFDAA978FAEA3C01.1 Target Package: ft256
Registration ID 210945993_0_0_712 Target Speed: -5
Date Generated 2014-12-17T15:32:58 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-3540M CPU @ 3.00GHz CPU Speed 2990 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 19-bit adder=1
 Comparators=8
  • 10-bit comparator greatequal=2
  • 10-bit comparator less=5
  • 11-bit comparator less=1
 Counters=2
  • 10-bit up counter=2
 Latches=1
  • 19-bit latch=1
 Registers=1
  • Flip-Flops=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=27
  • AGG_IO=27
  • AGG_SLICE=19
  • NUM_4_INPUT_LUT=35
  • NUM_BONDED_IOB=27
  • NUM_BUFGMUX=2
  • NUM_CYMUX=18
  • NUM_SLICEL=19
  • NUM_SLICE_FF=21
  • NUM_XOR=20
 		NetStatistics
  • NumNets_Active=71
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=11
  • NumNodesOfType_Active_CNTRLPIN=6
  • NumNodesOfType_Active_DOUBLE=33
  • NumNodesOfType_Active_DUMMY=96
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_GLOBAL=12
  • NumNodesOfType_Active_HUNIHEX=4
  • NumNodesOfType_Active_INPUT=110
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_OMUX=42
  • NumNodesOfType_Active_OUTPUT=43
  • NumNodesOfType_Active_PREBXBY=22
  • NumNodesOfType_Active_VFULLHEX=3
  • NumNodesOfType_Active_VUNIHEX=1
  • NumNodesOfType_Vcc_CNTRLPIN=2
  • NumNodesOfType_Vcc_INPUT=1
  • NumNodesOfType_Vcc_PREBXBY=1
  • NumNodesOfType_Vcc_VCCOUT=2
 SiteStatistics
  • IOB-DIFFM=11
  • IOB-DIFFS=11
  • SLICEL-SLICEM=9
 		SiteSummary
  • BUFGMUX=2
  • BUFGMUX_GCLKMUX=2
  • BUFGMUX_GCLK_BUFFER=2
  • IOB=27
  • IOB_INBUF=1
  • IOB_OUTBUF=26
  • IOB_PAD=27
  • SLICEL=19
  • SLICEL_CYMUXF=10
  • SLICEL_CYMUXG=8
  • SLICEL_F=18
  • SLICEL_F5MUX=3
  • SLICEL_FFX=10
  • SLICEL_FFY=11
  • SLICEL_G=17
  • SLICEL_GNDF=10
  • SLICEL_GNDG=8
  • SLICEL_XORF=10
  • SLICEL_XORG=10
 
Configuration Data
BUFGMUX
  • S=[S_INV:2] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:2]
  • S=[S_INV:2] [S:0]
 IOB
  • O1=[O1_INV:0] [O1:26]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:26]
 IOB_PAD
  • DRIVEATTRBOX=[12:26]
  • IOATTRBOX=[LVCMOS25:27]
  • SLEW=[SLOW:26]
 SLICEL
  • BX=[BX_INV:0] [BX:5]
  • BY=[BY:1] [BY_INV:0]
  • CE=[CE:5] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:8]
  • CLK=[CLK:11] [CLK_INV:0]
  • SR=[SR:1] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:10] [0_INV:0]
  • 1=[1_INV:0] [1:10]
 SLICEL_CYMUXG
  • 0=[0:8] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:3] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:5] [CE_INV:0]
  • CK=[CK:10] [CK_INV:0]
  • D=[D:10] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:10]
  • FFX_SR_ATTR=[SRLOW:10]
  • LATCH_OR_FF=[FF:10]
  • SYNC_ATTR=[ASYNC:10]
 SLICEL_FFY
  • CE=[CE:5] [CE_INV:0]
  • CK=[CK:11] [CK_INV:0]
  • D=[D:11] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:11]
  • FFY_SR_ATTR=[SRLOW:11]
  • LATCH_OR_FF=[FF:11]
  • SR=[SR:1] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:10] [SYNC:1]
 SLICEL_XORF
  • 1=[1_INV:0] [1:10]
 
Pin Data
BUFGMUX
  • I0=2
  • O=2
  • S=2
 BUFGMUX_GCLKMUX
  • I0=2
  • OUT=2
  • S=2
 BUFGMUX_GCLK_BUFFER
  • IN=2
  • OUT=2
 IOB
  • I=1
  • O1=26
  • PAD=27
 IOB_INBUF
  • IN=1
  • OUT=1
 IOB_OUTBUF
  • IN=26
  • OUT=26
 IOB_PAD
  • PAD=27
 SLICEL
  • BX=5
  • BY=1
  • CE=5
  • CIN=8
  • CLK=11
  • COUT=8
  • F1=15
  • F2=15
  • F3=6
  • F4=6
  • G1=17
  • G2=17
  • G3=9
  • G4=8
  • SR=1
  • X=8
  • XQ=10
  • Y=4
  • YQ=11
 SLICEL_CYMUXF
  • 0=10
  • 1=10
  • OUT=10
  • S0=10
 SLICEL_CYMUXG
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
 SLICEL_F
  • A1=15
  • A2=15
  • A3=6
  • A4=6
  • D=18
 SLICEL_F5MUX
  • F=3
  • G=3
  • OUT=3
  • S0=3
 SLICEL_FFX
  • CE=5
  • CK=10
  • D=10
  • Q=10
 SLICEL_FFY
  • CE=5
  • CK=11
  • D=11
  • Q=11
  • SR=1
 SLICEL_G
  • A1=17
  • A2=17
  • A3=9
  • A4=8
  • D=17
 SLICEL_GNDF
  • 0=10
 SLICEL_GNDG
  • 0=8
 SLICEL_XORF
  • 0=10
  • 1=10
  • O=10
 SLICEL_XORG
  • 0=10
  • 1=10
  • O=10
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1000-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 37 24 0 0 0 0 0
bitgen 28 28 0 0 0 0 0
map 34 32 0 0 0 0 0
ngdbuild 36 36 0 0 0 0 0
par 32 30 2 0 0 0 0
trce 30 30 0 0 0 0 0
xst 91 89 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=Modelsim-SE Verilog PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2014-12-16T17:16:04
PROP_intWbtProjectID=1BF1B53EA1BD4DB3BFDAA978FAEA3C01 PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_AutoTop=false PROP_DevFamily=Spartan3
PROP_DevDevice=xc3s1000 PROP_DevFamilyPMName=spartan3
PROP_DevPackage=ft256 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-5 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=4
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=10 NGDBUILD_NUM_FDCE=10
NGDBUILD_NUM_FDR=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_LUT2=17 NGDBUILD_NUM_LUT3_D=1
NGDBUILD_NUM_LUT4=12 NGDBUILD_NUM_LUT4_D=2 NGDBUILD_NUM_MUXCY=18 NGDBUILD_NUM_MUXF5=3
NGDBUILD_NUM_OBUF=26 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=20
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FDC=10 NGDBUILD_NUM_FDCE=10 NGDBUILD_NUM_FDR=1
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_LUT2=17 NGDBUILD_NUM_LUT3_D=1
NGDBUILD_NUM_LUT4=12 NGDBUILD_NUM_LUT4_D=2 NGDBUILD_NUM_MUXCY=18 NGDBUILD_NUM_MUXF5=3
NGDBUILD_NUM_OBUF=26 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=20
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s1000-5-ft256 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5