testMem Project Status (12/17/2014 - 15:53:26)
Project File: Final.xise Parser Errors: No Errors
Module Name: vgaTop Implementation State: Synthesized
Target Device: xc3s1000-5ft256
  • Errors:
  
Product Version:ISE 14.7
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Dec 16 18:27:23 2014   
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateWed Dec 17 15:32:58 2014
WebTalk Log FileOut of DateWed Dec 17 15:33:22 2014

Date Generated: 12/17/2014 - 15:53:26