ActualTop Project Status (12/17/2014 - 15:56:03)
Project File:	TestIt.xise	Parser Errors:	No Errors
Module Name:	ActualTop	Implementation State:	Programming File Generated
Target Device:	xc3s1000-5ft256	Errors:	No Errors
Product Version:	ISE 14.7	Warnings:	No Warnings
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	21	15,360	1%
Number of 4 input LUTs	36	15,360	1%
Number of occupied Slices	29	7,680	1%
Number of Slices containing only related logic	29	29	100%
Number of Slices containing unrelated logic	0	29	0%
Total Number of 4 input LUTs	54	15,360	1%
Number used as logic	36
Number used as a route-thru	18
Number of bonded IOBs	6	173	3%
Number of BUFGMUXs	2	8	25%
Average Fanout of Non-Clock Nets	3.16

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Wed Dec 17 15:55:15 2014	0	0	0
Translation Report	Current	Wed Dec 17 15:55:23 2014	0	0	0
Map Report	Current	Wed Dec 17 15:55:27 2014	0	0	2 Infos (0 new)
Place and Route Report	Current	Wed Dec 17 15:55:33 2014	0	0	2 Infos (0 new)
Power Report
Post-PAR Static Timing Report	Current	Wed Dec 17 15:55:36 2014	0	0	6 Infos (0 new)
Bitgen Report	Current	Wed Dec 17 15:55:41 2014	0	0	1 Info (0 new)

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Wed Dec 17 15:55:41 2014
WebTalk Log File	Current	Wed Dec 17 15:56:02 2014

Date Generated: 12/17/2014 - 15:56:03