| Project Statistics |
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PROP_Enable_Message_Filtering=false |
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PROP_LastAppliedGoal=Balanced |
| PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
| PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=Modelsim-SE Verilog |
| PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
| PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
| PROP_intProjectCreationTimestamp=2014-12-16T19:23:45 |
PROP_intWbtProjectID=ADF88CDC5B7F43C484AB6833F26FD38B |
| PROP_intWbtProjectIteration=8 |
PROP_intWorkingDirLocWRTProjDir=Same |
| PROP_intWorkingDirUsed=No |
PROP_xilxBitgStart_IntDone=true |
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PROP_DevFamily=Spartan3 |
| PROP_DevDevice=xc3s1000 |
PROP_DevFamilyPMName=spartan3 |
| PROP_DevPackage=ft256 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
| PROP_DevSpeed=-5 |
PROP_PreferredLanguage=Verilog |
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FILE_VERILOG=2 |