vgaTop Project Status (12/17/2014 - 02:08:36)
Project File:	TestIt.xise	Parser Errors:	No Errors
Module Name:	vgaTop	Implementation State:	Programming File Not Generated
Target Device:	xc3s1000-5ft256	Errors:
Product Version:	ISE 14.7	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue Dec 16 19:25:16 2014
Translation Report
Map Report
Place and Route Report
CPLD Fitter Report (Text)
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Wed Dec 17 02:08:16 2014
WebTalk Log File	Current	Wed Dec 17 02:08:36 2014

Date Generated: 12/17/2014 - 02:08:36