| SineSynth Project Status (12/16/2014 - 02:02:16) | |||
| Project File: | NoteGeneratorCopy.xise | Parser Errors: | No Errors |
| Module Name: | InstructionMemory | Implementation State: | Synthesized |
| Target Device: | xc3s1000-5ft256 |
|
|
| Product Version: | ISE 14.7 |
|
|
| Design Goal: | Balanced |
|
|
| Design Strategy: | Xilinx Default (unlocked) |
|
|
| Environment: | System Settings |
|
|
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Mon Dec 15 23:10:04 2014 | ||||
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Report | Out of Date | Tue Dec 16 01:03:31 2014 | |
| WebTalk Log File | Out of Date | Tue Dec 16 01:03:36 2014 | |