Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s1000
Project ID (random number) 41804946b74d4b479f8236ba537b6b51.E5120F5DF98A43D6BAF31F998A21BD90.24 Target Package: ft256
Registration ID 210941524_0_0_633 Target Speed: -5
Date Generated 2014-12-16T09:54:01 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-2760QM CPU @ 2.40GHz CPU Speed 2394 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=2
  • 11-bit adder=1
  • 13-bit adder=1
Comparators=2
  • 13-bit comparator equal=2
Counters=2
  • 13-bit up counter=1
  • 16-bit up counter=1
Logic shifters=13
  • 26-bit shifter logical left=13
RAMs=1
  • 1998x29-bit single-port block RAM=1
Registers=11
  • Flip-Flops=11
MiscellaneousStatistics
  • AGG_BONDED_IO=9
  • AGG_IO=9
  • AGG_SLICE=118
  • NUM_4_INPUT_LUT=226
  • NUM_BONDED_IOB=9
  • NUM_BUFGMUX=1
  • NUM_CYMUX=71
  • NUM_LUT_RT=43
  • NUM_RAMB16=5
  • NUM_SLICEL=118
  • NUM_SLICE_FF=66
  • NUM_XOR=68
  • Xilinx Core dds_compiler_v4_0, Xilinx CORE Generator 14.7=1
NetStatistics
  • NumNets_Active=295
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=60
  • NumNodesOfType_Active_CLKPIN=43
  • NumNodesOfType_Active_CNTRLPIN=95
  • NumNodesOfType_Active_DOUBLE=572
  • NumNodesOfType_Active_DUMMY=686
  • NumNodesOfType_Active_DUMMYBANK=38
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_GLOBAL=22
  • NumNodesOfType_Active_HFULLHEX=8
  • NumNodesOfType_Active_HLONG=3
  • NumNodesOfType_Active_HUNIHEX=138
  • NumNodesOfType_Active_INPUT=746
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_OMUX=168
  • NumNodesOfType_Active_OUTPUT=285
  • NumNodesOfType_Active_PREBXBY=193
  • NumNodesOfType_Active_VFULLHEX=19
  • NumNodesOfType_Active_VLONG=3
  • NumNodesOfType_Active_VUNIHEX=41
  • NumNodesOfType_Gnd_BRAMADDR=7
  • NumNodesOfType_Gnd_CNTRLPIN=19
  • NumNodesOfType_Gnd_DOUBLE=24
  • NumNodesOfType_Gnd_INPUT=4
  • NumNodesOfType_Gnd_OMUX=15
  • NumNodesOfType_Gnd_OUTPUT=8
  • NumNodesOfType_Gnd_PREBXBY=5
SiteStatistics
  • IOB-DIFFM=4
  • IOB-DIFFS=3
  • SLICEL-SLICEM=60
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IOB=9
  • IOB_INBUF=1
  • IOB_OUTBUF=8
  • IOB_PAD=9
  • RAMB16=5
  • RAMB16_RAMB16=5
  • RAMB16_RAMB16A=5
  • RAMB16_RAMB16B=1
  • SLICEL=118
  • SLICEL_C1VDD=3
  • SLICEL_CYMUXF=37
  • SLICEL_CYMUXG=34
  • SLICEL_F=117
  • SLICEL_F5MUX=18
  • SLICEL_FFX=37
  • SLICEL_FFY=29
  • SLICEL_G=109
  • SLICEL_GNDF=21
  • SLICEL_GNDG=22
  • SLICEL_XORF=35
  • SLICEL_XORG=33
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IOB
  • O1=[O1_INV:0] [O1:8]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:8]
IOB_PAD
  • DRIVEATTRBOX=[12:8]
  • IOATTRBOX=[LVCMOS25:9]
  • SLEW=[SLOW:8]
RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:5]
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • ENA=[ENA_INV:0] [ENA:5]
  • ENB=[ENB_INV:0] [ENB:1]
  • SSRA=[SSRA_INV:0] [SSRA:5]
  • SSRB=[SSRB_INV:0] [SSRB:1]
  • WEA=[WEA:5] [WEA_INV:0]
  • WEB=[WEB:1] [WEB_INV:0]
RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:5]
  • ENA=[ENA_INV:0] [ENA:5]
  • PORTA_ATTR=[8192X2:1] [2048X9:4]
  • SSRA=[SSRA_INV:0] [SSRA:5]
  • WEA=[WEA:5] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:4] [READ_FIRST:1]
RAMB16_RAMB16B
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • PORTB_ATTR=[2048X9:1]
  • SSRB=[SSRB_INV:0] [SSRB:1]
  • WEB=[WEB:1] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:1]
SLICEL
  • BX=[BX_INV:0] [BX:23]
  • CE=[CE:16] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:34]
  • CLK=[CLK:37] [CLK_INV:0]
  • SR=[SR:15] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:37] [0_INV:0]
  • 1=[1_INV:0] [1:37]
SLICEL_CYMUXG
  • 0=[0:34] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:18] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:43] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:16] [CE_INV:0]
  • CK=[CK:37] [CK_INV:0]
  • D=[D:37] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:37]
  • FFX_SR_ATTR=[SRLOW:37]
  • LATCH_OR_FF=[FF:37]
  • SR=[SR:15] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:22] [SYNC:15]
SLICEL_FFY
  • CE=[CE:8] [CE_INV:0]
  • CK=[CK:29] [CK_INV:0]
  • D=[D:29] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:29]
  • FFY_SR_ATTR=[SRLOW:29]
  • LATCH_OR_FF=[FF:29]
  • SR=[SR:14] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:15] [SYNC:14]
SLICEL_XORF
  • 1=[1_INV:0] [1:35]
SLICEM
  • BX=[BX_INV:0] [BX:18]
  • BY=[BY:18] [BY_INV:0]
SLICEM_F
  • LUT_OR_MEM=[LUT:18]
SLICEM_F5MUX
  • S0=[S0:18] [S0_INV:0]
SLICEM_F6MUX
  • S0=[S0:18] [S0_INV:0]
SLICEM_G
  • LUT_OR_MEM=[LUT:18]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IOB
  • I=1
  • O1=8
  • PAD=9
IOB_INBUF
  • IN=1
  • OUT=1
IOB_OUTBUF
  • IN=8
  • OUT=8
IOB_PAD
  • PAD=9
RAMB16
  • ADDRA1=1
  • ADDRA10=5
  • ADDRA11=5
  • ADDRA12=5
  • ADDRA13=5
  • ADDRA2=1
  • ADDRA3=5
  • ADDRA4=5
  • ADDRA5=5
  • ADDRA6=5
  • ADDRA7=5
  • ADDRA8=5
  • ADDRA9=5
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=5
  • CLKB=1
  • DOA0=5
  • DOA1=5
  • DOA2=4
  • DOA3=4
  • DOA4=4
  • DOA5=4
  • DOA6=4
  • DOA7=4
  • DOPA0=3
  • ENA=5
  • ENB=1
  • SSRA=5
  • SSRB=1
  • WEA=5
  • WEB=1
RAMB16_RAMB16
  • ADDRA=5
  • ADDRB=1
  • DIA=5
  • DIB=1
  • DOA=5
  • DOB=1
RAMB16_RAMB16A
  • ADDRA=5
  • ADDRA1=1
  • ADDRA10=5
  • ADDRA11=5
  • ADDRA12=5
  • ADDRA13=5
  • ADDRA2=1
  • ADDRA3=5
  • ADDRA4=5
  • ADDRA5=5
  • ADDRA6=5
  • ADDRA7=5
  • ADDRA8=5
  • ADDRA9=5
  • CLKA=5
  • DIA=5
  • DOA=5
  • DOA0=5
  • DOA1=5
  • DOA2=4
  • DOA3=4
  • DOA4=4
  • DOA5=4
  • DOA6=4
  • DOA7=4
  • DOPA0=3
  • ENA=5
  • SSRA=5
  • WEA=5
RAMB16_RAMB16B
  • ADDRB=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKB=1
  • DIB=1
  • DOB=1
  • ENB=1
  • SSRB=1
  • WEB=1
SLICEL
  • BX=23
  • CE=16
  • CIN=34
  • CLK=37
  • COUT=34
  • F1=116
  • F2=92
  • F3=84
  • F4=72
  • G1=108
  • G2=86
  • G3=74
  • G4=53
  • SR=15
  • X=85
  • XB=1
  • XQ=37
  • Y=61
  • YQ=29
SLICEL_C1VDD
  • 1=3
SLICEL_CYMUXF
  • 0=37
  • 1=37
  • OUT=37
  • S0=37
SLICEL_CYMUXG
  • 0=34
  • 1=34
  • OUT=34
  • S0=34
SLICEL_F
  • A1=116
  • A2=92
  • A3=84
  • A4=72
  • D=117
SLICEL_F5MUX
  • F=18
  • G=18
  • OUT=18
  • S0=18
SLICEL_F6MUX
  • 0=43
  • 1=43
  • OUT=43
  • S0=43
SLICEL_FFX
  • CE=16
  • CK=37
  • D=37
  • Q=37
  • SR=15
SLICEL_FFY
  • CE=8
  • CK=29
  • D=29
  • Q=29
  • SR=14
SLICEL_G
  • A1=108
  • A2=86
  • A3=74
  • A4=53
  • D=109
SLICEL_GNDF
  • 0=21
SLICEL_GNDG
  • 0=22
SLICEL_XORF
  • 0=35
  • 1=35
  • O=35
SLICEL_XORG
  • 0=33
  • 1=33
  • O=33
SLICEM
  • BX=18
  • BY=18
  • F1=18
  • F2=18
  • F3=16
  • F4=10
  • F5=18
  • FX=9
  • FXINA=18
  • FXINB=18
  • G1=18
  • G2=17
  • G3=16
  • G4=8
  • Y=9
SLICEM_F
  • A1=18
  • A2=18
  • A3=16
  • A4=10
  • D=18
SLICEM_F5MUX
  • F=18
  • G=18
  • OUT=18
  • S0=18
SLICEM_F6MUX
  • 0=18
  • 1=18
  • OUT=18
  • S0=18
SLICEM_G
  • A1=18
  • A2=17
  • A3=16
  • A4=8
  • D=18
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 54 52 0 0 0 0 0
bitgen 46 46 0 0 0 0 0
map 61 58 0 0 0 0 0
ngdbuild 63 62 0 0 0 0 0
par 58 58 0 0 0 0 0
trce 58 58 0 0 0 0 0
xps 1 1 0 0 0 0 0
xst 159 144 0 0 0 0 0
 
Help Statistics
Search words with results
command line ( 1 ) command line option ( 1 )
synthesis property ( 1 ) use new parser ( 1 )
Unsuccessful Search words
use_new_parser ( 1 )
Help files
/doc/usenglish/isehelp/ise_p_using_cmd_line_options.htm ( 1 ) /doc/usenglish/isehelp/ite_c_overview.htm ( 1 )
/doc/usenglish/isehelp/pim_db_commsetupdlg.htm ( 1 ) /doc/usenglish/isehelp/pn_c_tip_of_day.htm ( 1 )
/doc/usenglish/isehelp/pn_r_design_panel.htm ( 2 ) /doc/usenglish/isehelp/pp_db_simulation_model_properties.htm ( 1 )
/doc/usenglish/isehelp/pp_db_xst_synthesis_options.htm ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/runSynth
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2013-12-15T23:29:22
PROP_intWbtProjectID=E5120F5DF98A43D6BAF31F998A21BD90 PROP_intWbtProjectIteration=24
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_selectedSimRootSourceNode_behav=work.runSynth
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan3 PROP_DevDevice=xc3s1000
PROP_DevFamilyPMName=spartan3 PROP_DevPackage=ft256
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-5
PROP_PreferredLanguage=Verilog FILE_NGC=1
FILE_UCF=1 FILE_USERDOC=2
FILE_VERILOG=2
 
Core Statistics
Core Type=dds_compiler_v4_0
c_accumulator_width=26 c_amplitude=0 c_channels=1 c_has_ce=0
c_has_channel_index=0 c_has_phase_out=0 c_has_phasegen=1 c_has_rdy=0
c_has_rfd=0 c_has_sclr=0 c_has_sincos=1 c_latency=-1
c_mem_type=1 c_negative_cosine=0 c_negative_sine=0 c_noise_shaping=0
c_optimise_goal=0 c_output_width=8 c_outputs_required=0 c_phase_angle_width=8
c_phase_increment=3 c_phase_increment_value=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 c_phase_offset=0 c_phase_offset_value=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0
c_por_mode=0 c_use_dsp48=0 c_xdevicefamily=spartan3
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=27 NGDBUILD_NUM_FDE=11 NGDBUILD_NUM_FDR=16
NGDBUILD_NUM_FDRE=13 NGDBUILD_NUM_GND=2 NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT1=39
NGDBUILD_NUM_LUT2=43 NGDBUILD_NUM_LUT3=25 NGDBUILD_NUM_LUT3_D=3 NGDBUILD_NUM_LUT3_L=3
NGDBUILD_NUM_LUT4=114 NGDBUILD_NUM_LUT4_D=3 NGDBUILD_NUM_LUT4_L=3 NGDBUILD_NUM_MUXCY=72
NGDBUILD_NUM_MUXF5=18 NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_VCC=2 NGDBUILD_NUM_XORCY=68
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=27 NGDBUILD_NUM_FDE=11 NGDBUILD_NUM_FDR=16
NGDBUILD_NUM_FDRE=13 NGDBUILD_NUM_GND=2 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=3
NGDBUILD_NUM_LUT1=39 NGDBUILD_NUM_LUT2=43 NGDBUILD_NUM_LUT3=25 NGDBUILD_NUM_LUT3_D=3
NGDBUILD_NUM_LUT3_L=3 NGDBUILD_NUM_LUT4=114 NGDBUILD_NUM_LUT4_D=3 NGDBUILD_NUM_LUT4_L=3
NGDBUILD_NUM_MUXCY=72 NGDBUILD_NUM_MUXF5=18 NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_RAMB16_S2=1
NGDBUILD_NUM_RAMB16_S9=3 NGDBUILD_NUM_RAMB16_S9_S9=1 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=2
NGDBUILD_NUM_XORCY=68
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s1000-5-ft256 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-verilog2001=YES -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -mult_style=Auto -iobuf=YES -max_fanout=100000
-bufg=8 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Yes -use_sync_set=Yes -use_sync_reset=Yes -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5