SineSynth Project Status (12/16/2014 - 02:02:16) | |||
Project File: | NoteGeneratorCopy.xise | Parser Errors: | No Errors |
Module Name: | sineSynth | Implementation State: | Synthesized |
Target Device: | xc3s1000-5ft256 |
|
|
Product Version: | ISE 14.7 |
|
|
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Tue Dec 16 01:16:19 2014 | ||||
Translation Report | Out of Date | Mon Dec 15 23:37:00 2014 | ||||
Map Report | Out of Date | Mon Dec 15 23:37:14 2014 | ||||
Place and Route Report | Out of Date | Mon Dec 15 23:37:26 2014 | ||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | Mon Dec 15 23:37:30 2014 | ||||
Bitgen Report | Out of Date | Mon Dec 15 23:41:01 2014 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Out of Date | Tue Dec 16 01:03:31 2014 | |
WebTalk Log File | Out of Date | Tue Dec 16 01:03:36 2014 |