SineSynth Project Status (12/16/2014 - 02:02:16)
Project File: NoteGeneratorCopy.xise Parser Errors: No Errors
Module Name: sineSynth Implementation State: Synthesized
Target Device: xc3s1000-5ft256
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Dec 16 01:16:19 2014   
Translation ReportOut of DateMon Dec 15 23:37:00 2014   
Map ReportOut of DateMon Dec 15 23:37:14 2014   
Place and Route ReportOut of DateMon Dec 15 23:37:26 2014   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportOut of DateMon Dec 15 23:37:30 2014   
Bitgen ReportOut of DateMon Dec 15 23:41:01 2014   
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateTue Dec 16 01:03:31 2014
WebTalk Log FileOut of DateTue Dec 16 01:03:36 2014

Date Generated: 12/16/2014 - 02:02:16