SineSynth Project Status (12/16/2014 - 02:02:16)
Project File: NoteGeneratorCopy.xise Parser Errors: No Errors
Module Name: TopLevelSynth Implementation State: Synthesized
Target Device: xc3s1000-5ft256
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 38 15,360 1%  
Number of 4 input LUTs 852 15,360 5%  
Number of occupied Slices 494 7,680 6%  
    Number of Slices containing only related logic 494 494 100%  
    Number of Slices containing unrelated logic 0 494 0%  
Total Number of 4 input LUTs 878 15,360 5%  
    Number used as logic 852      
    Number used as a route-thru 26      
Number of bonded IOBs 9 173 5%  
Number of RAMB16s 1 24 4%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 4.51      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Dec 16 00:31:22 2014   
Translation ReportCurrentTue Dec 16 00:36:24 2014   
Map ReportCurrentTue Dec 16 00:36:30 2014   
Place and Route ReportCurrentTue Dec 16 00:36:39 2014   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentTue Dec 16 00:36:43 2014   
Bitgen ReportCurrentTue Dec 16 00:40:10 2014   
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateTue Dec 16 01:03:31 2014
WebTalk Log FileOut of DateTue Dec 16 01:03:36 2014

Date Generated: 12/16/2014 - 02:02:16