2014:lcd_driver_on_an_fpga
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2014:lcd_driver_on_an_fpga [2014/12/16 06:36] snorthway |
2014:lcd_driver_on_an_fpga [2014/12/16 06:40] (current) dimitdim |
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| | {{ :2014:unicorn_dust.jpg?direct |}} | | | {{ :2014:unicorn_dust.jpg?direct |}} | | ||
| - | | Highlights from the Adafruit library code | | + | | Figure 2: Highlights from the Adafruit library code | |
| 5. There are about 6 different combinations of these in Adafruit's library alone based on which version of the screen you have. For ours, it was the Rcmd1, Rcmd2red and Rcmd3 sets. | 5. There are about 6 different combinations of these in Adafruit's library alone based on which version of the screen you have. For ours, it was the Rcmd1, Rcmd2red and Rcmd3 sets. | ||
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| 8. Colors are represented in two bytes according to the following diagram (from the huge datasheet): | 8. Colors are represented in two bytes according to the following diagram (from the huge datasheet): | ||
| - | {{ :2014:05h.png?direct |}} | + | |{{ :2014:05h.png?direct |}}| |
| - | Of course, this is one of MANY options set by 0x3A (ST7735_COLMOD). | + | | Figure 3: Of course, this is one of MANY options set by 0x3A (ST7735_COLMOD). | |
| 9. They are placed in consecutive order starting from the left-hand top-most pixel in the drawing area. [[https://drive.google.com/file/d/0BxPpLHO-t5J7bzU5NnRpalllWGs/view?usp=sharing|Here's an example.]] | 9. They are placed in consecutive order starting from the left-hand top-most pixel in the drawing area. [[https://drive.google.com/file/d/0BxPpLHO-t5J7bzU5NnRpalllWGs/view?usp=sharing|Here's an example.]] | ||
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| | {{ :2014:blockdiagram.jpg?direct |}} | | | {{ :2014:blockdiagram.jpg?direct |}} | | ||
| - | | Block diagram of Verilog implementation | | + | | Figure 4: Block diagram of Verilog implementation | |
| The following sections discuss the functions of each block. | The following sections discuss the functions of each block. | ||
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| Another thing that tripped us up a bit was the issue of timing in Verilog. For an LCD screen to work, the timing has to be exactly correct or nothing will look right. We had several instances of signals happening one clock cycle off from other signals, and this was because we used always *@(posedge clk)" for almost every module initially. The solution to this was usually either "always @(*)" or using the edge of one of the other timing signals. | Another thing that tripped us up a bit was the issue of timing in Verilog. For an LCD screen to work, the timing has to be exactly correct or nothing will look right. We had several instances of signals happening one clock cycle off from other signals, and this was because we used always *@(posedge clk)" for almost every module initially. The solution to this was usually either "always @(*)" or using the edge of one of the other timing signals. | ||
| + | |||
| + | ---- | ||
| + | |||
| + | ==== Finishing the Job ==== | ||
| + | |||
| + | The first step for anyone trying to pick up the pieces would be to try to put this on an FPGA. All the | ||
| + | |||
| + | Verilog (complete with Cat) is on GitHub (see bottom of page) as well as in this [[https://github.com/dimitdim/pineapple/blob/master/verilog.zip?raw=true|ZIP file]]. To build, | ||
| + | they should be imported into a new ISE project. There is also a working project on GitHub under | ||
| + | /strawberry. If more testing is necessary, a few Arduino simulations are also on GitHub, under | ||
| + | /ArduinoTests. Code for image conversion can be found under /images. | ||
| + | The screen needs to be connected the the FPGA as follows: | ||
| + | |||
| + | LITE -> External 5V supply with common GND | ||
| + | |||
| + | MISO -> N/A | ||
| + | |||
| + | SCK -> gpioBank1[3] | ||
| + | |||
| + | MOSI-> gpioBank1[0] | ||
| + | |||
| + | TFT_CS -> gpioBank1[1] | ||
| + | |||
| + | SD_CS -> N/A | ||
| + | |||
| + | D/C -> gpioBank1[2] | ||
| + | |||
| + | RESET -> gpioBank2[0] | ||
| + | |||
| + | VCC -> External 5V supply with common GND | ||
| + | |||
| + | GND -> GND | ||
| + | |||
| + | The next step we intended for this project was attaching a camera to the FPGA and streaming pictures and/or video to the screen. The camera we researched is the [[http://www.voit.nl/docs/OV7670.pdf|OV7670]]. This seems to be a good [[http://embeddedprogrammer.blogspot.com/2012/07/hacking-ov7670-camera-module-sccb-cheat.html|starting point]]. | ||
| ---- | ---- | ||
| We're on GitHub! - [[https://github.com/dimitdim/pineapple]] | We're on GitHub! - [[https://github.com/dimitdim/pineapple]] | ||
2014/lcd_driver_on_an_fpga.1418729766.txt.gz · Last modified: 2014/12/16 06:36 by snorthway
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