2014:vga_on_fpga
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2014:vga_on_fpga [2014/12/18 11:29] cwallace |
2014:vga_on_fpga [2014/12/18 11:35] (current) cwallace |
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| + | This waveform shows how each signal should look, the pixel clock is orders of magnitude faster than the horizontal sync, and that is orders of magnitude faster than the vertical sync. You should also notice that at the end and beginning of each sync signal the RGB values should be zero. | ||
| Reality: | Reality: | ||
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| 3. In both directories the relevant file is “Vgatop.v” the module top can be implemented in XIlinx,most files in those directories are for test, but may be of assistance to you. | 3. In both directories the relevant file is “Vgatop.v” the module top can be implemented in XIlinx,most files in those directories are for test, but may be of assistance to you. | ||
| 4. If attempting to implement the data memory with your own image, you must download the python script mentioned earlier and modify the data memory file such that it loads from that file. | 4. If attempting to implement the data memory with your own image, you must download the python script mentioned earlier and modify the data memory file such that it loads from that file. | ||
| + | 5. Before you implement any of these, it is a good idea to read our difficulties section. | ||
| Workplan: | Workplan: | ||
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| Due to VGA’s analog signal, we should have allocated more time than the 48 man hours we spent on the project. This is because there is a lot more to go wrong and test, and for us a large amount of time disappeared debugging the FPGA when the problem was the circuitry connecting it to the VGA port. | Due to VGA’s analog signal, we should have allocated more time than the 48 man hours we spent on the project. This is because there is a lot more to go wrong and test, and for us a large amount of time disappeared debugging the FPGA when the problem was the circuitry connecting it to the VGA port. | ||
2014/vga_on_fpga.1418920172.txt.gz · Last modified: 2014/12/18 11:29 by cwallace
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