projects:optimization_of_a_pipelined_cpu
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projects:optimization_of_a_pipelined_cpu [2013/12/19 23:39] cbailey |
projects:optimization_of_a_pipelined_cpu [2013/12/20 00:23] (current) jhanford [Optimizing a Pipelined CPU] |
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| **Brendan Caporaletti, Chelsea Bailey, Jeffrey Hanford** | **Brendan Caporaletti, Chelsea Bailey, Jeffrey Hanford** | ||
| + | Code: [[https://www.dropbox.com/s/2ulskrgce5xltpq/CPU_ResourceFiles.zip]] | ||
| ===== The Vision ===== | ===== The Vision ===== | ||
| Line 26: | Line 27: | ||
| As part of our pipeline optimization, the six comparators at the bottom of the diagram check to see if later registers being requested in later phases of the CPU are the same as the ones being operated on. If the registers are the same, the ID phase outputs the updated data instead of the original, outdated information in that register that has not yet been written back to. | As part of our pipeline optimization, the six comparators at the bottom of the diagram check to see if later registers being requested in later phases of the CPU are the same as the ones being operated on. If the registers are the same, the ID phase outputs the updated data instead of the original, outdated information in that register that has not yet been written back to. | ||
| - | In a jump operation, **BRENDAN PUT STUFF HERE THAT IS GOOD AND ACCURATE ABOUT ALL THE JUMPS**the amount it should jump by is contained within 16 bits of the opcode. This register is fed through a sign extender, shifted by two, added to the current PC number and output to the next phase of the CPU. | + | In a jump operation, the amount it should jump by is contained within 16 bits of the opcode. This immediate is fed through a sign extender, shifted by two, added to the current PC number and output to the next previous of the CPU. If this is a jump and link, Jal and RegWrite are put high. WriteReg allows us to write the PC to the register file. Jal selects the PC+4 to replace the ALUOut and to replace the WriteReg with register 31. If this is a normal Jump Jal is set high but RegWrite is not. Therefore the register will not be set despite Jal being on. Forwarding ignores register 0 in order to avoid forwarding of Jumps writing to register 31. In either case Jal forces PC to jump to the Branch location. |
| If WriteEnable is high, the number being fed into WD3 is written to the write register A3 from the writeback phase. | If WriteEnable is high, the number being fed into WD3 is written to the write register A3 from the writeback phase. | ||
| - | **[TALK ABOUT BRANCH COMPARATOR THING]** | + | In order for us to avoid the number of No-Ops that incorrect branching would entail, we moved our BNE comparator into the ID phase. This way we only have to cancel a single instruction upon branching. Our method of branch prediction in this model is static. We always assume that we are not branching, until the comparator tells us otherwise. |
| ==== EX ==== | ==== EX ==== | ||
| {{:projects:ex.png?800|}} | {{:projects:ex.png?800|}} | ||
| Line 53: | Line 54: | ||
| In our original CPU design, we treated branching in the same method as jumping, which was a different implementation from MIPS. To make our CPU fully MIPS compliant we had to add concatenation into the ID phase where we do our jumping. According to MIPS, branch commands are based on a delta where as jump commands require a target destination. The jump machine codes provides 26 bits which when concatenated with two 0's in the low order bits and the 4 highest order bits of the PC, provides the jump destination. | In our original CPU design, we treated branching in the same method as jumping, which was a different implementation from MIPS. To make our CPU fully MIPS compliant we had to add concatenation into the ID phase where we do our jumping. According to MIPS, branch commands are based on a delta where as jump commands require a target destination. The jump machine codes provides 26 bits which when concatenated with two 0's in the low order bits and the 4 highest order bits of the PC, provides the jump destination. | ||
| - | **EXPLAIN JAL JR 11111 00000 THING** | + | In order to use all 26 bits of immediate normal Jump operations must forcibly have their WriteReg set to 0 as to avoid errors in forwarding. This is why the RegWrite line, being the difference between Jump and Jal, controls whether Jal will force WriteReg to be 31 or 0. |
| - | + | ||
| - | **EXPLAIN JALE LINE MUX** | + | |
| {{:projects:pipelinedcpu_v2.0.png?800|}} | {{:projects:pipelinedcpu_v2.0.png?800|}} | ||
| Line 104: | Line 103: | ||
| E = C | E = C | ||
| - | {{:projects:pipelinedcpu_v4.0.png?900|}} | + | {{:projects:pipelinedcpu_v4final.png?900|}} |
| - | ===== Timing Analysis ===== | + | |
| - | ==== Version 1 (Original)==== | + | |
| - | + | ||
| - | Version 1 corresponds to the pipelined CPU we use for our base. It is the CPU we tested by synthesizing using XILINX. The data from that report is as follows: | + | |
| - | + | ||
| - | ^ Phase ^ Clockspeed (ns) ^ | + | |
| - | | IF |27.364| | + | |
| - | | ID |21.51| | + | |
| - | | EX |22.587| | + | |
| - | | MEM |27.779| | + | |
| - | | WB |<20| | + | |
| - | **Throughput:** | ||
| - | ==== Version 2 (MIPS Compliant)==== | ||
| - | ==== Version 3 (Jump Forward)==== | ||
| - | ==== Version 4 (Dynamic Branching)==== | ||
| ===== Reflection ===== | ===== Reflection ===== | ||
projects/optimization_of_a_pipelined_cpu.1387514370.txt.gz · Last modified: 2013/12/19 23:39 by cbailey
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