2014:large_integer_exponentiation
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2014:large_integer_exponentiation [2014/12/17 21:09] promnius |
2014:large_integer_exponentiation [2014/12/17 21:25] (current) promnius |
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| ==Schematics== | ==Schematics== | ||
| - | {{:2014:img_0329.jpg?200|}} | + | {{:2014:img_0329_b.jpg?500|}} |
| - | {{:2014:img_0327.jpg?200|}} | + | |
| - | EXPLANATION HERE | + | {{:2014:img_0332.jpg?500|}} |
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| + | In the top image, a basic input conditioning circuit is seen. It doesn't implement any real standard, but it gets the job done. A and B can be clocked in serially, with a chip select pin to disable computation while new values are clocked in. My implementation doesn't have a 'calculation finished' flag, but it wouldn't be too difficult to add. Instead, my implementation relies on the fact that X^0 = 1, and Y*1 = Y. Therefore, once every bit has been shifted out (so B = 0), further computations won't change the result at all. | ||
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| + | In the bottom image, the basic computation circuit is seen. bits are serially clocked out of B, which are then used to determine if result is increased or not. If not, it is multiplied by 1. If so, it is multiplied by the 'A' register, which is equal to A^N where N is some power of 2. The 'A' register is increased each clock cycle by multiplying A by itself (giving the geometric series of A^N for N= some power of 2). | ||
| ===Difficulties=== | ===Difficulties=== | ||
2014/large_integer_exponentiation.1418868597.txt.gz · Last modified: 2014/12/17 21:09 by promnius
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